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zilog w orldwide headquarters ? 532 race street ? san jose, ca 95126 t elephone: 408.558.8500 ? f ax: 408.558.8300 ? www .zilog.com z8 f amily of microcontrollers z8 cpu user manual um001602-0904
z8 family of microcontrollers user manual um001602-0904 ii this publication is subject to replacement by a later edition. t o determine whether a later edition e xists, or to request copies of publications, contact : zilog w orld wide headquarters 532 race street san jose, ca 95126 t elephone: 408.558.8500 f ax: 408.558.8300 www .zilog.com document disclaimer zilog is a re gistered trademark of zilog inc. in the united states and in other countries. all other products and/or service names mentioned herein may be trademarks of the companies with which the y are associated. ? 2004 by zilog, inc. all rights reserv ed. information in this publication concerning the de vices, applications, or technology described is intended to suggest possible uses and may be superseded. zilog, inc. does no t assume liability for or pr o vide a represent a tion of a ccura cy of the informa tion, devices, or t echn ology described in this document . zilog also does no t assume liability for intellectu al pr oper ty infringement rela ted in any manner t o use of informa tion, devices, or t echn ology described herein or o ther wise. de vices sold by zilog, inc. are co v ered by w arranty and limitation of liability pro visions appearing in the zilog, inc. t erms and conditions of sale. zilog, inc. mak es no w arranty of merchantability or ? tness for an y purpose except with the e xpress written appro v al of zilog, use of information, de vices, or technology as critical components of life support systems is not authorized. no licenses are con v e yed, implicitly or otherwise, by this document under an y intellectual property rights.
z8 cpu user manual um001602-0904 revision history iii revision history each instance in t able 1 re? ects a change to this document from its pre vi - ous re vision. t o see more detail, click the appropriate link in the table. t able 1. revision history of this document date revision level section description page # sept. 2 004 02 formatted to current publication standards all
z8 family of microcontrollers user manual revision history um001602-0904 iv
z8 cpu user manual um001602-0904 table of contents v t able of contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii i l ist of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii z8 cpu product overvie w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 key f eatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 product development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 z8 cpu standard register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 general-purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ram protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 working register groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 z8 expanded register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 z8 control and peripheral registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 standard z8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 expanded z8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 z8 external memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 external data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 z8 stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 frequency control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 sclk tclk divide-by-16 select . . . . . . . . . . . . . . . . . . . . . . . . . 34 external clock divide-by-two . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 oscillator control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
z8 family of microcontrollers user manual table of contents um001602-0904 vi oscillator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 indications of an unreliable design . . . . . . . . . . . . . . . . . . . . . . . . . . 38 circuit board design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 crystals and resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 lc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 reset pin, internal por operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 watchCdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 power-on-reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 input and output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 general i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 read/write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 handshake operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 general i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 read/write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 handshake operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 general port i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 read/write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 handshake operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 general port i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 read/write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 special functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 port handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
z8 cpu user manual um001602-0904 table of contents vii i/o port reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 full reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 analog comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 comparator description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 comparator programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 comparator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 comparator definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 open-drain configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 low emi emission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 input protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 z8 cmos autolatche s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 autolatch m odel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 counters and timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 prescalers and counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 counter/timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 load and enable count bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 prescaler operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 t out modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 t in modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 external clock input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 gated internal clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 triggered input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 retriggerable input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 cascading counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
z8 family of microcontrollers user manual table of contents um001602-0904 viii interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 external interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 internal interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 interrupt request register logic and timing . . . . . . . . . . . . . . . . . . . . . 141 interrupt initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 interrupt priority register initialization . . . . . . . . . . . . . . . . . . . . . . 143 interrupt mask register initialization . . . . . . . . . . . . . . . . . . . . . . . . 145 interrupt request register initialization . . . . . . . . . . . . . . . . . . . . . . 147 irq software interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 vectored processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 vectored interrupt cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 nesting of vectored interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 polled processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 power-down modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 halt mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 stop mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 stop-mode recovery register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 serial input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 uart introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 uart bit-rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 uart receiver operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 receiver shift register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 overwrites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 transmitter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 overwrites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 uart reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
z8 cpu user manual um001602-0904 table of contents ix serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 spi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 spi compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 spi clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 receive character available and overrun . . . . . . . . . . . . . . . . . . . . . . . 182 external interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 external addressing configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 external stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 address strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 data strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 extended bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 instruction timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 z8 reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 processor flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 carry flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 zero flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 sign flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 overflow flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 decimal adjust flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 half carry flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 condition codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 notation and binary encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 assembly language syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 z8 instruction summar y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 op code map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
z8 family of microcontrollers user manual table of contents um001602-0904 x instruction description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 customer feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
z8 cpu user manual um001602-0904 list of figures xi list of f igures figure 1. z8 cpu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2. 16-bit register addressing . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. accessing individual bits (example) . . . . . . . . . . . . . . . . . 9 figure 4. working register addressing examples . . . . . . . . . . . . . 12 figure 5. register pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. expanded register file architecture . . . . . . . . . . . . . . . . 15 figure 7. register pointer example . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 8. z8 program memory map . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 9. external memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 10. stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 11. stack operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 12. z8 ? cpu clock circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 13. stop-mode recovery register . . . . . . . . . . . . . . . . . . . . . 34 figure 14. external clock circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 15. port configuration register . . . . . . . . . . . . . . . . . . . . . . . 36 figure 16. pierce oscillator with internal feedback circuit . . . . . . . 37 figure 17. circuit board design rules . . . . . . . . . . . . . . . . . . . . . . . 40 figure 18. crystal/ceramic resonator oscillator . . . . . . . . . . . . . . . . 41 figure 19. lc clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 20. external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 21. rc clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 22. reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
z8 family of microcontrollers user manual list of figures um001602-0904 xii figure 23. example of external power-on reset circuit . . . . . . . . . . 50 figure 24. example of z8 reset with reset pin, wdt, smr, a nd por . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 25. example of z8 reset with wdt, smr, and por . . . . . . 54 figure 26. example of z8 watchCdog timer mode register . . . . . . 56 figure 27. example of z8 with simple smr and por . . . . . . . . . . . 59 figure 28. i/o ports and mode registers . . . . . . . . . . . . . . . . . . . . . . 62 figure 29. ports 0, 1, 2 generic block diagram . . . . . . . . . . . . . . . . 64 figure 30. port 0 configuration with open-drain capability, a utolatch, and schmitt-trigger . . . . . . . . . . . . . . . . . . . . . 66 figure 31. port 0 configuration with ttl level shifter . . . . . . . . . . 67 figure 32. port 0 i/o operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 33. port 0 handshake operation . . . . . . . . . . . . . . . . . . . . . . . 69 figure 34. port 1 configuration with open-drain capability, a utolatch, and schmitt-trigger . . . . . . . . . . . . . . . . . . . . . 70 figure 35. port 1 configuration with ttl level shifter . . . . . . . . . . 71 figure 36. port 1 i/o operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 37. handshake operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 38. port 2 i/o mode configuration . . . . . . . . . . . . . . . . . . . . . 74 figure 39. port 2 configuration with open-drain capability, a utolatch, and schmitt-trigger . . . . . . . . . . . . . . . . . . . . . 75 figure 40. port 2 configuration with ttl level shifter . . . . . . . . . . 76 figure 41. port 2 configuration with open-drain capability, a utolatch, schmitt-trigger and spi . . . . . . . . . . . . . . . . . 77 figure 42. port 2 handshake configuration . . . . . . . . . . . . . . . . . . . . 79
z8 cpu user manual um001602-0904 list of figures xiii figure 43. port 2 handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 44. port 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 45. port 3 configuration with comparator, autolatch, and schmitt-trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 46. port 3 configuration with comparator . . . . . . . . . . . . . . . 84 figure 47. port 3 configuration with spi and comparator outputs . 86 figure 48. port 3 configuration with ttl level shifter and a utolatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 49. port 3 mode register configuration . . . . . . . . . . . . . . . . . 88 figure 50. z8 input handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 51. z8 output handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 52. output strobed handshake on port 2 . . . . . . . . . . . . . . . . 94 figure 53. input strobed handshake on port 2 . . . . . . . . . . . . . . . . . 94 figure 54. port 0/1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 55. port 2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 56. port 3 mode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 57. port 3 input analog selection . . . . . . . . . . . . . . . . . . . . . . 99 figure 58. port 3 comparator output selection . . . . . . . . . . . . . . . . 100 figure 59. port configuration of comparator inputs on p31, p32, a nd p33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 60. port 3 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 61. port 2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 62. port configuration register . . . . . . . . . . . . . . . . . . . . . . 106 figure 63. diode input protection . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 64. otp diode input protection . . . . . . . . . . . . . . . . . . . . . . 110
z8 family of microcontrollers user manual list of figures um001602-0904 xiv figure 65. simplified cmos z8 i/o circuit . . . . . . . . . . . . . . . . . . 111 figure 66. autolatch e quivalent circuit . . . . . . . . . . . . . . . . . . . . . . 113 figure 67. effect of pulldown resistors on autolatche s . . . . . . . . . 114 figure 68. counter/timer block diagram . . . . . . . . . . . . . . . . . . . . 116 figure 69. counter/timer register map . . . . . . . . . . . . . . . . . . . . . . 118 figure 70. prescaler 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 71. prescaler 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 72. counter/timer 0 and 1 registers . . . . . . . . . . . . . . . . . . . 119 figure 73. timer mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 74. starting the count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 75. counting modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 76. timer mode register (t out operation) . . . . . . . . . . . . . 124 figure 77. port 3 mode register (t out operation) . . . . . . . . . . . . . 125 figure 78. t0 and t1 output through t out . . . . . . . . . . . . . . . . . . 126 figure 79. internal clock output through t out . . . . . . . . . . . . . . . 127 figure 80. timer mode register (t in operation) . . . . . . . . . . . . . . 128 figure 81. prescaler 1 register (t in operation) . . . . . . . . . . . . . . . . 128 figure 82. external clock input mode . . . . . . . . . . . . . . . . . . . . . . . 129 figure 83. gated clock input mode . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 84. triggered clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 85. cascaded counter/timers . . . . . . . . . . . . . . . . . . . . . . . . 132 figure 86. counter/timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 figure 87. prescaler 1 register reset . . . . . . . . . . . . . . . . . . . . . . . . 133 figure 88. prescaler 0 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
z8 cpu user manual um001602-0904 list of figures xv figure 89. timer mode register reset . . . . . . . . . . . . . . . . . . . . . . 135 figure 90. interrupt control registers . . . . . . . . . . . . . . . . . . . . . . . 137 figure 91. interrupt block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 92. interrupt sources irq0-irq2 block diagram . . . . . . . . 140 figure 93. interrupt source irq3 block diagram . . . . . . . . . . . . . . 141 figure 94. irq register logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 figure 95. interrupt request timing . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 96. interrupt priority register . . . . . . . . . . . . . . . . . . . . . . . . 144 figure 97. interrupt mask register . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 98. interrupt request register . . . . . . . . . . . . . . . . . . . . . . . . 148 figure 99. irq reset functional logic diagram . . . . . . . . . . . . . . . 149 figure 100. effects of an interrupt on the stack . . . . . . . . . . . . . . . . . 151 figure 101. interrupt vectoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 figure 102. z8 interrupt acknowledge timing . . . . . . . . . . . . . . . . . 153 figure 103. stop-mode recovery register . . . . . . . . . . . . . . . . . . . . 160 figure 104. stop-mode recovery source . . . . . . . . . . . . . . . . . . . . . 163 figure 105. uart block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 106. port 3 mode register and bit-rate generation . . . . . . . 167 figure 107. bit rate divide chain . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 108. prescaler 0 register bit-rate generation . . . . . . . . . . . . 169 figure 109. timer mode register bit rate generation . . . . . . . . . . . 169 figure 110. receiver timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 111. receiver data formats . . . . . . . . . . . . . . . . . . . . . . . . . . 172 figure 112. port 3 mode register parity . . . . . . . . . . . . . . . . . . . . . . 173
z8 family of microcontrollers user manual list of figures um001602-0904 xvi figure 113. transmitter data formats . . . . . . . . . . . . . . . . . . . . . . . . 175 figure 114. sio register reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 figure 115. p3m register reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 figure 116. spi control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 figure 117. spi system configuration . . . . . . . . . . . . . . . . . . . . . . . . 181 figure 118. spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 figure 119. spi logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 figure 120. spi data in/out configuration . . . . . . . . . . . . . . . . . . . . 184 figure 121. spi clock/spi slave select output configuration . . . . . 185 figure 122. z8 c pu external interface pins . . . . . . . . . . . . . . . . . . . 187 figure 123. external address configuration . . . . . . . . . . . . . . . . . . . 190 figure 124. z8 stack selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 figure 125. port 3 data memory operation . . . . . . . . . . . . . . . . . . . . 192 figure 126. external instruction fetch or memory read cycle . . . . . 193 figure 127. external memory write cycle . . . . . . . . . . . . . . . . . . . . . 194 figure 128. extended external instruction fetch or memory read c ycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 figure 129. extended external memory write cycle . . . . . . . . . . . . 197 figure 130. extended bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 figure 131. instruction cycle timing (1-byte instructions) . . . . . . . 199 figure 132. instruction cycle timing (2- and 3-byte instructions) . . 200 figure 133. z8 flag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 figure 134. op code map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
z8 cpu user manual um001602-0904 list of tables xvii list of t ables table 1. revision history of this document . . . . . . . . . . . . . . . . . . . iii table 2. zilog general-purpose microcontroller product family . 4 table 3. z8 standard register file . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. working register groups . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. erf bank address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 6. register pointer access example . . . . . . . . . . . . . . . . . . . 18 table 7. e rf bank c access example . . . . . . . . . . . . . . . . . . . . . . 20 table 8. z8 expanded register file bank layout . . . . . . . . . . . . . 20 table 9. expanded register file register bank c . . . . . . . . . . . . . 23 table 10. expanded register file bank 0 . . . . . . . . . . . . . . . . . . . . . 24 table 11. expanded register file bank f . . . . . . . . . . . . . . . . . . . . . 25 table 12. crystal/resonator characteristics . . . . . . . . . . . . . . . . . . . 41 table 13. sample control and peripheral register reset values ( erf bank 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 14. expanded register file bank 0 reset values at reset . 51 table 15. sample expanded register file bank c reset values . . . 51 table 16. sample expanded register file bank f reset values . . . 52 table 17. time-out period of the wdt . . . . . . . . . . . . . . . . . . . . . . 57 table 18. port 3 line functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 19. interrupt types, sources, and vectors . . . . . . . . . . . . . . 139 table 20. interrupt priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 21. interrupt group priority . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 22. irq register configuratio n . . . . . . . . . . . . . . . . . . . . . . 1 49 table 23. s top-mode r ecovery source . . . . . . . . . . . . . . . . . . . . . 161 table 24. uart register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 25. bit rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
z8 family of microcontrollers user manual list of tables um001602-0904 xviii table 26. spi pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 27. load instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 28. arithmetic instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 202 table 29. logical instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 table 30. program control instructions . . . . . . . . . . . . . . . . . . . . . 202 table 31. bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . 203 table 32. block transfer instructions . . . . . . . . . . . . . . . . . . . . . . . 203 table 33. rotate and shift instructions . . . . . . . . . . . . . . . . . . . . . . 204 table 34. cpu control instructions . . . . . . . . . . . . . . . . . . . . . . . . 204 table 35. z8 flag definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 table 36. flag settings definitions . . . . . . . . . . . . . . . . . . . . . . . . . 208 table 37. condition codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 table 38. notational shorthand . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 39. additional symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 table 40. summary of z8 instruction set . . . . . . . . . . . . . . . . . . . . 213 table 41. summary of z8 a ddress modes . . . . . . . . . . . . . . . . . . . 221 table 42. process manipulation functions . . . . . . . . . . . . . . . . . . . 223
z8 cpu user manual um001602-0904 z8 cpu product overvie w 1 z8 cpu product ov erview t he zilog z8 microcontroller (mcu) product line continues to e xpand with ne w product introductions. zilog mcu products are tar geted for cost-sensiti v e, high-v olume applications including consumer , automoti v e, security , and hv a c. it includes r om-based products geared for high- v olume production (where softw are is stable) and one-time programma - ble (o tp) equi v alents for prototyping as well as v olume production where time to mark et or code ? e xibility is critical ( see t able 1 on page 4 ) . a v ariety of packaging options are a v ailable including plastic dip , soic, plcc, and qfp . a generalized z8 cpu ? block diagram is sho wn in figure 1 . the same on-chip peripherals are used across the mcu product line with the pri - mary dif ferences being the amount of r om/ram, number of i/o lines present, and packaging/temperature ranges a v ailable. this allo ws code written for one mcu de vice to be easily ported to another f amily mem - ber . key features general-purpose register f il e . e v ery ram re gister acts lik e an accu - mulator , speeding instruction e x ecution and maximizing coding ef ? - cienc y . w orking re gister groups allo w f ast conte xt switching. flexible i/ o . i /o byte, nibble, and/or bit programmable as inputs or out - puts. outputs are softw are programmable as open-drain or pushCpull on a port basis. inputs are schmitt-triggered with autolatche s to hold unused inputs at a kno wn v oltage state. analog input s . t hree input pins are softw are programmable as digital or analog inputs. when in a nalog mode, tw o comparator inputs are pro vided with a common reference input. these inputs are ideal for a v ariety of common functions, including threshold le v el detection, analog-to-digital
z8 family of microcontrollers user manual z8 cpu product overvie w um001602-0904 2 con v ersion, and short circuit detection. each analog input pro vides a unique maskable interrupt input. t imer/counte r . t he t imer/counter (t/c) c onsists of a programmable 6- bit prescaler and 8-bit do wncounter , with maskable interrupt upon end-of- count. softw are controls t/c load/start/stop, countdo wn read (at an y time on the ? y), and maskable end-of-count interrupt. special functions a v ail - able include t in (e xternal counter input, e xternal g ate input, or e xternal trigger input) and t out (e xternal access to timer output or the internal system clock.) these special functions allo w accurate hardw are input pulse measurement and output w a v eform generation. interrupt s . t here are six v ectored interrupt sources with softw are-pro - grammable enable and priority for each of the six sources. w atchCdog t ime r . a n internal w atchCdog t imer (wdt ) circuit is included as a f ail-safe mechanism so that if softw are strays outside the bounds of normal operation, the wdt will time-out and reset the mcu. t o maximize circuit rob ustness and reliability , the def ault wdt clock source is an internal rc circuit (isolated from the de vice clock source). auto reset/low-v oltage pr otectio n . a ll f amily de vices ha v e internal po wer -on reset. r om de vices add lo w-v oltage protection. lo w-v oltage protection ensures the mcu is in a kno wn state at all times (in acti v e r un mode or reset) without e xternal hardw are (or a de vice reset pin). low-emi operatio n . m ode is programmable via softw are or as a mask option. this ne w option pro vides for reduced radiated emission via clock and output dri v e circuit changes. low-powe r . c mos with tw o standby modes; st op and hal t . full z8 instruction se t . f orty-eight basic instructions, supported by six addressing modes with the ability to operate on bits, nibbles, bytes, and w ords.
z8 cpu user manual um001602-0904 z8 cpu product overvie w 3 figure 1. z8 cpu block diagram port 3 counter/ t imers (2) interrupt control analog comparators (2) output input alu flag register pointer register file 256 x 8-bit machine t iming & instruction control reset , wdt , por prg. memory 512/k x 8-bit program counter v cc gnd xtal address or i/o (nibble programmable) port 2 port 0 port 1 as ds r/ w reset 4 4 8 address/data or i/o (byte programmable) i/o (bit programmable)
z8 family of microcontrollers user manual z8 cpu product overvie w um001602-0904 4 product development support t he z8 ? mcu p roduct line is fully supported with a range of cross assemblers, c compilers, icebo x emulators, single and g ang o tp/ epr om programmers, and softw are simulators. the z86c cp01zem lo w-cost z8 ccp? real-time emulator/programmer kit w as designed speci? cally to support all of the p roducts outlined in t able 1 . t able 1. zilog general-purpose microcontroller product family product rom/ ram i/0 t/c an int wdt por v bo rc speed (mhz) pin count z86c03 512/60 14 1 2 6 f y y y 8 18 z86e03 512/60 14 1 2 6 f y n y 8 18 z86c04 1k/124 14 2 2 6 f y y y 8 18 z86e04 1k/124 14 2 2 6 f y n y 8 18 z86c06 1k/124 14 2 2 6 p y y y 12 18 z86e06 1k/124 14 2 2 6 p y n y 12 18 z86c08 2k/124 14 2 2 6 f y y y 12 18 z86e08 2k/124 14 2 2 6 f y n y 12 18 Z86C30 4k/236 24 2 2 6 p y y y 12 28 z86e30 4k/236 24 2 2 6 p y n y 12 28 z86c31 2k/124 24 2 2 6 p y y y 8 28 z86e31 2k/124 24 2 2 6 p y n y 8 28 z86c40 4k/236 32 2 2 6 p y y y 16 40/44 z86e40 4k/236 32 2 2 6 p y n y 16 40/44 *note: z86cxx signify rom devices; 86xx signify eprom devices; f = f ixed; p = p rogrammable
z8 cpu user manual um001602-0904 z8 cpu product overvie w 5 th e z86 ccp01zem kit comes with: ? z8 ccp ev aluation board ? z8 ccp po wer cable ? zilog de v eloper s studio (zds) cd-r om , including w indo ws- based gui host softw are ? 1999 zilog t echnical library ? z8 ccp user manual a z8 ccp emulator accessory kit (z8ccp00za c) is also a v ailable and pro vides an rs-232 cable and po wer cable along with the 28- and 40- pin zif sock ets and 28- and 40- pin tar get connector cables required to emu - late/program 28/40 pin de vices.
z8 family of microcontrollers user manual z8 cpu product overvie w um001602-0904 6
z8 cpu user manual um001602-0904 address space 7 address space intr oduction f our address spaces are a v ailable for the z8 ? cpu : ? th e z8 ? standard re gister file contains addresses for peripheral, control, all general-purpose, and all i/o port re gisters. this is the def ault re gister ? le speci? cation. ? the z8 ? expanded re gister file (erf) contains addresses for con - trol and data re gisters for additional peripherals/features. ? z8 e xternal program memory contains addresses for all memory loca - tions ha ving e x ecutable code and/or data. ? z8 e xternal data memory contains addresses for all memory locations that hold data only , whether internal or e xternal. z8 cpu standard register file the z8 ? standard re gister file totals up to 256 consecuti v e bytes (re gis - ters). the re gister ? le consists of 4 i/o ports ( 00h?3h ), 236 general- purpose re gisters ( 04h?fh ), and 16 control re gisters ( f0h?fh ). t able 2 s ho ws the layout of the re gister ? le, including re gister names, locations, and identi? ers. t able 2. z8 standard register file hex address register identifier register description ff spl stack pointer low byte fe sph stack pointer high byte fd rp register pointer
z8 family of microcontrollers user manual address space um001602-0904 8 re gisters can be accessed as either 8-bit or 16-bit re gisters using direct, indirect, or inde x ed addressing. all 236 general-purpose re gisters can be fc flags program control flags fb imr interrupt mask register f a irq interrupt request register f9 ipr interrupt priority register f8 p01m port 0C1 m ode register f7 p3m port 3 mode register f6 p2m port 2 mode register f5 pre0 t0 prescaler f4 t0 t imer/counter 0 f3 pre1 t1 prescaler f2 t1 t imer/counter 1 f1 tmr t imer mode f0 sio serial i/o ef r239 general-purpose registers (gpr) 04 r4 03 p3 port 3 02 p2 port 2 01 p1 port 1 00 p0 port 0 t able 2. z8 standard register file (continued) hex address register identifier register description
z8 cpu user manual um001602-0904 address space 9 referenced or modi? ed by an y instruction that accesses an 8-bit re gister , without the requirement for special instructions. re gisters accessed as 16 bits are treated as e v en-odd re gister pairs (there are 118 v alid pairs). in this case, the data s most signi? cant byte (msb) is stored in the e v en numbered re gister , while the least signi? cant byte (lsb) goes into the ne xt higher odd numbered re gister . see figure 2 . by using a logical instruction and a mask, indi vidual bits within re gisters can be accessed for bit set, bit clear , bit complement, or bit test opera - tions. f or e xample, the instruction and r15, mask performs a bit clear operation. figure 3 s ho ws this e xample. figure 2. 16-bit register ad dressing figure 3. accessing individual bits (example) msb lsb rn r n+1 n = e ven address 0 1 0 1 0 0 0 0 r15 0 1 1 1 0 0 0 0 1 1 0 1 1 1 1 1 mask r15 and r15, d fh ; clear bit 5 of working register 15
z8 family of microcontrollers user manual address space um001602-0904 10 when instructions are e x ecuted, re gisters are read when de? ned as sources and written when de? ned as destinations. all general-purpose re gisters function as accumulators, address pointers, inde x re gisters, stack areas, or scratch pad memory . general-purpose registers general-purpose re gisters (gpr) are unde? ned after the de vice is po w - ered up. the re gisters k eep their last v alue after an y reset, as long as the reset occurs in the v cc v oltage-speci? ed operating range. it will not k eep its last state from a v lv reset if v cc drops belo w 1.8v . re gisters in bank e0-ef may only be accessed through the w orking re gis - ter and indirect addressing modes. direct access cannot be used because the 4-bit w orking re gister address mode already uses the format [e | dst], where dst represents the w orking re gister number from 0h to fh. ram protect the upper portion of the re gister ? le address space 80h to efh (e xcluding the control re gisters) may be protected from reading and writing. the ram protect bit option is mask-programmable and is selected by the cus - tomer when the r om code is submitted. after the mask option is selected, the user acti v ates this feature from the internal r om code to turn of f/on the ram protect by loading either a 0 or 1 into the imr re gis - ter , bit d6. a 1 in d6 enables ram protect. only de vices that use re gis - ters 80h to efh of fer this feature. working register groups z8 instructions can access 8-bit re gisters and re gister pairs (16-bit w ords) using either 4-bit or 8-bit address ? elds. 8-bit address ? elds refer to the actual address of the re gister . f or e xample, re gister 58h is accessed by calling upon its 8-bit binary equi v alent, 01011000 ( 58h ). w ith 4-bit addressing, the re gister ? le is logically di vided into 16 w ork - ing re gister groups of 16 re gisters each, as sho wn in t able 3 . these 16 note:
z8 cpu user manual um001602-0904 address space 11 re gisters are kno wn as w orking re gisters. a re gister pointer (one of the control re gisters, fdh ) contains the base address of the acti v e w orking re gister group. the high nibble of the re gister pointer determines the current w orking re gister group. when accessing one of the w orking re gisters, the 4-bit address of the w orking re gister is combined within the upper four bits (high nibble) of the re gister pointer , thus forming the 8-bit actual address. figure 4 i llus - trates this operation. because w orking re gisters are typically speci? ed by short format instructions, there are fe wer bytes of code required, which reduces e x ecution time. in addition, when processing interrupts or chang - ing tasks, the re gister pointer speeds conte xt switching. a special set re gister pointer (srp) instruction sets the contents of the re gister pointer . t able 3. w orking register groups register pointe r ( f dh) h igh nibble w orkin g r egister grou p (hex) actua l r egister s (hex) 1 1 1 1 b f f0Cff 1 1 10 b e e0Cef 1 101 b d d0Cdf 1 100 b c c0Ccf 101 1 b b b0Cbf 1010 b a a0Caf 1001 b 9 90C9f 1000 b 8 80C8f 01 1 1 b 7 70C7f 01 10 b 6 60C6f 0101 b 5 50C5f 0100 b 4 40C4f
z8 family of microcontrollers user manual address space um001602-0904 12 001 1 b 3 30C3f 0010 b 2 20C2f 0001 b 1 10C1f 0000 b 0 00C0f figure 4. w orking register addressing examples t able 3. w orking register groups (continued) register pointe r ( f dh) h igh nibble w orkin g r egister grou p (hex) actua l r egister s (hex) 0 1 1 1 0 1 1 0 register pointer ( fdh) , standard register file 0 1 1 1 0 0 0 0 1 1 0 1 1 1 1 1 inc r6 ( in struction, sh ort fo rmat) actual re gister address (76h)
z8 cpu user manual um001602-0904 address space 13 error conditions re gisters in the z8 ? standard re gister file must be correctly used because certain conditions produce inconsistent results and should be a v oided. ? re gisters f3h and f5h C f9h are write-only re gisters. if an attempt is made to read these re gisters, ffh is returned. reading an y write-only re gister will return ffh . *note: the full register file is shown. please refer to the selected device product specification for actual file size. figure 5. register pointer ff f0 r7 r6 r5 r4 r3 r2 r1 r0 specified working register group r253 i/o ports working register group 1 working register group 0 working register group f ef 80 7f 70 6f 60 5f 50 4f 40 3f 30 2f 20 1f 10 0f 00 the lower nibble of the register file address (provided by the instruction) points to the specified register. the upper nibble of the register file address, provided by the register pointer, specifies the active working-register group. (register pointer) r15 to r0 r15 to r4 r3 to r0
z8 family of microcontrollers user manual address space um001602-0904 14 ? when re gister fdh (re gister pointer) is read, the least signi? cant four bits (lo wer nibble) will indicate the current expanded re gister file bank. (example: 0000 indicates the standard re gister file, while 1010 indicates expanded re gister file bank a.) ? when ports 0 and 1 are de? ned as address outputs, re gisters 00h and 01h will return 1s in each address bit location when read. ? writing to bits that are de? ned as timer output, serial output, or hand - shak e output will ha v e no ef fect. ? th e z8 ? cpu instruction djnz uses an y general-purpose w orking re gister as a counter . ? logical instructions such as or and and require that the current contents of the operand be read. the y therefore will not function properly on write-only re gisters. ? the wdtmr re gister must be written within the ? rst 60 internal sys - tem clocks (sclk) of operation after a reset. z8 expanded register file the standard re gister ? le of the z8 ? cpu has been e xpanded to form 16 expanded re gister file (erf) banks , as sho wn in figure 6 . each erf bank consists of up to 256 re gisters (the same amount as in the standard re gister file) that can then be di vided into 16 w orking re gister groups. this e xpansion allo ws for access to additional feature/peripheral control and data re gisters.
z8 cpu user manual um001602-0904 address space 15 *note: the fully implemented register file is shown. please refer to the specific product specification for actual register file archi - tecture implemented. figure 6. expanded register file architecture z8 register file (f) 0f wdtmr expanded register ff 0f 7f f0 00 expanded register file bank (f) (f) 0e reserved (f) 0d reserved (f) 0c reserved (f) 0b smr (f ) 0a reserved (f) 09 reserved (f) 08 reserved (f) 07 reserved (f) 06 reserved (f) 05 reserved (f) 04 reserved (f) 03 reserved (f) 0e reserved (f) 02 reserved (f) 01 reserved (f) 00 pcon (0) 0f gpr expanded register file bank (0) (0) 0e gpr (0) 0d gpr (0) 0c gpr (0) 0b gpr (0) 0a gpr (0) 09 gpr (0) 08 gpr (0) 07 gpr (0) 06 gpr (0) 05 gpr (0) 04 gpr (0) 03 p3 (0) 02 p2 (0) 01 p1 (0) 00 p0 (c) 0f reserved expanded register file bank (c) (c) 0e reserved (c) 0d reserved (c) 0c reserved (c) 0b reserved (c) 0a reserved (c) 09 reserved (c) 08 reserved (c) 07 reserved (c) 06 reserved (c) 05 reserved (c) 04 reserved (c) 03 reserved (c) 02 scon (c) 01 rxbuf (c) 00 scomp d7 d6 d5 d4 d3 d2 d1 d0 working register group pointer group pointer register pointer
z8 family of microcontrollers user manual address space um001602-0904 16 currently , three out of the possible sixteen z8 erf banks ha v e been implemented. erf bank 0, also kno wn as the z8 ? standard re gister file, has all 256 bytes de? ne d, as sho wn in figure 7 . only w orking re gister group 0 (re gister addresses 00h to 0fh ) ha v e been de? ned for erf bank c and erf bank f ( see t able 4 ) . all other w orking re gister groups in erf banks c and f , as well as the remaining thirteen erf banks, are not implemented. all are reserv ed for future use. when an erf bank is selected, re gister addresses 00h to 0fh access those sixteen erf bank re gistersin ef fect replacing the ? rst sixteen locations o f the z8 ? sta ndard re gister file. f or e xample, if erf bank c is selected, the z8 ? s tandard re gisters 00h through 0fh are no longer accessible. re gisters 00h through 0fh are no w the 16 re gisters from erf bank c, w orking re gister group 0. no other z8 standard re gisters are af fected because only w orking re gister group 0 is implemented in erf bank c. access to the erf is accomplished through the re gister pointer ( fdh ). the lo wer nibble of the re gister pointer determines the erf bank while the upper nibble determines the w orking re gister group within the re gis - ter ? le , as figure 7 sho ws. figure 7. register p ointer example 0 1 1 1 1 1 0 0 working select erf bank c h register group expanded register bank working register group 7 h
z8 cpu user manual um001602-0904 address space 17 the v alue of the lo wer nibble in the re gister pointer ( fdh ) corresponds to the erf bank identi? cation. t able 4 s ho ws the lo wer nibble v alue and the re gister ? le assigned to it. t able 4. erf bank address register pointe r ( f dh) l ow nibble he x register file 0000 b 0 z8 standard register file .* 0001 b 1 expanded register file bank 1 . 0010 b 2 expanded register file bank 2 . 001 1 b 3 expanded register file bank 3 .. 0100 b 4 expanded register file bank 4 0101 b 5 expanded register file bank 5 .. 01 10 b 6 expanded register file bank 6 01 1 1 b 7 expanded register file bank 7 .. 1000 b 8 expanded register file bank 8 1001 b 9 expanded register file bank 9 .. 1010 b a expanded register file bank a 101 1 b b expanded register file bank b . 1 100 b c expanded register file bank c . 1 101 b d expanded register file bank d .. 1 1 10 b e expanded register file bank e 1 1 1 1 b f expanded register file bank f . *note: the z8 ? standard register file is equivalent to expanded register file bank 0.
z8 family of microcontrollers user manual address space um001602-0904 18 the upper nibble of the re gister pointer selects which group of 16 bytes in the re gister file, out of the 2 56 total bytes , will be accessed as w orking re gisters . t able 5 sho ws an e xample. t able 5. register pointer access example r253 rp = 00h ;erf bank 0, w orking reg. group 0. r0 = p ort 0 = 00h r1 = p ort 1 = 01h r2 = p ort 2 = 02h r3 = p ort 3 = 03h r1 1 = g pr 0bh r15 = g pr 0fh i f r 253 rp = 0fh ;erf bank f , w orking reg. group 0. r0 = p con = 00h r1 = r eserved = 01h r2 = r eserved = 02h r1 1 = s mr = 0bh r15 = w dtmr = 0fh
z8 cpu user manual um001602-0904 address space 19 because enabling an erf bank (c or f) only changes re gister addresses 00h to 0fh , the w orking re gister pointer can be used to access either the selected erf bank (bank c or f , w orking re gister group 0) or the z8 ? standard re gister file (erf bank 0, w orking re gister groups 1 through f). when an erf bank other than bank 0 is enabled, the ? rst 16 bytes of the z8 ? standard re gister file (i/o ports 0 to 3, groups 4 to f) are no longer accessible (the selected erf bank, re gisters 00h to 0fh are accessed instead). it is important to re-initialize the re gister pointer to enable erf bank 0 when these re gisters are required for use. the spi re gister is mapped into erf bank c. access is easily done using the e xample in t able 6 . if r 253 rp = ffh ;erf bank f , w orking reg. group f . 00h = p con r0 = s i0 01h = r eserved r1 = t mr 02h = r eserved ... r2 = t 1 0bh = s mr ... r15 = s pl 0fh = w dtmr t able 5. register pointer access example (continued)
z8 family of microcontrollers user manual address space um001602-0904 20 t able 6. e rf bank c access example ld rp , #0 ch ;select erf bank c working ;register group 0 for access. ld r2,#xx ;access scon ld r1, #xx ;access rxbuf ld rp , # 00h ;select erf bank 0 so i/o ports ;are again accessible. t able 7. z8 expanded register file bank layout expande d r egister fil e b ank erf f h pcon, smr, wdt , (00h, 0bh, 0fh), w orking register group 0 o nly implemented. e h not im plemente d (reserved) d h not im plemente d (reserved) c h spi registers: scomp , r xbuf , s con ( 00h, 01h, 02h), w orking register group 0 o nly implemented. b h not im plemente d (reserved) a h not im plemente d (reserved) 9 h not im plemente d (reserved) 8 h not im plemente d (reserved) 7 h not im plemente d (reserved) 6 h not im plemente d (reserved) 5 h not im plemente d (reserved)
z8 cpu user manual um001602-0904 address space 21 please refer to the speci? c product speci? cation to determine the abo v e re gisters are implemented. z8 contr ol and peripheral registers standard z8 registers the standard z8 control re gisters go v ern the operation of the cpu. an y instruction which references the re gister ? le can access these control re g - isters. a v ailable control re gisters are: ? interrupt priority re gister (ipr) ? interrupt mask re gister (imr) ? interrupt request re gister (irq) ? program control flags (fla gs) ? re gister pointer (rp) ? stack pointer high-byte (sph) ? stack pointer lo w-byte (spl) 4 h not im plemente d (reserved) 3 h not im plemente d (reserved) 2 h not im plemente d (reserved) 1 h not im plemente d (reserved) 0 h z8 ports 0, 1, 2, 3 , a nd general-purpose register s 04h t o e fh, and control register s f0h t o f fh. t able 7. z8 expanded register file bank layout expande d r egister fil e b ank erf
z8 family of microcontrollers user manual address space um001602-0904 22 th e z8 ? cpu uses a 16-bit program counter (pc) to determine the sequence of current program instructions. the pc is not an addressable re gister . peripheral re gisters are used to transfer data, con? gure the operating mode, and control the operation of the on-chip peripherals. an y instruc - tion that references the re gister ? le can access the peripheral re gisters. the peripheral re gisters are: ? serial i/o (sio) ? t imer mode (tmr) ? t imer/counter 0 (t0) ? t0 prescaler (pre0) ? t imer/counter 1 (t1) ? t1 prescaler (pre1) ? port 0C1 mode (p01m) ? port 2 mode (p2m) ? port 3 mode (p3m) in addition, the four port re gisters (p0Cp3) are considered to be peripheral re gisters. expanded z8 registers the e xpanded z8 control re gisters go v ern the operation of additional fea - tures or peripherals. an y instruction which references the re gister ? le can access these re gisters. the erf contains the control re gisters for wdt , port control, serial peripheral interf ace (spi), and the smr functions. figure 6 on page 15 s ho ws the layout of the re gister banks in the erf . re gister bank c in the erf consists of the re gisters for the spi. t able 8 s ho ws the re gisters within erf bank c, w orking re gister group 0.
z8 cpu user manual um001602-0904 address space 23 t able 8. expanded register file register bank c w r group 0 register f unction w orkin g r egister f reserved r15 e reserved r14 d reserved r13 c reserved r12 b reserved r1 1 a reserved r10 9 reserved r9 8 reserved r8 7 reserved r7 6 reserved r6 5 reserved r5 4 reserved r4 3 reserved r3 2 spi control (scon) r2 1 spi tx/rx data (roxburgh) r1 0 spi compare (scomp) r0
z8 family of microcontrollers user manual address space um001602-0904 24 w orking re gister group 0 in erf bank 0 consists of the re gisters for z8 general-purpose re gisters and ports. t able 9 s ho ws the re gisters within this group. t able 9. expanded register file bank 0 w r group 0 register f unction w orkin g r egister f general-purpose register r15 e general-purpose register r14 d general-purpose register r13 c general-purpose register r12 b general-purpose register r1 1 a general-purpose register r10 9 general-purpose register r9 8 general-purpose register r8 7 general-purpose register r7 6 general-purpose register r6 5 general-purpose register r5 4 general-purpose register r4 3 port 3 r3 2 port 2 r2 1 port 1 r1 0 port 0 r0
z8 cpu user manual um001602-0904 address space 25 w orking re gister group 0 in erf bank f consists of the control re gisters for st op mode, wdt , and port control. t able 10 s ho ws the re gisters within this group. t able 10. expanded register file bank f w r group 0 register f unction w orkin g r egister f wdtmr r15 e reserved r14 d reserved r13 c reserved r12 b smr r1 1 a reserved r10 9 reserved r9 8 reserved r8 7 reserved r7 6 reserved r6 5 reserved r5 4 reserved r4 3 reserved r3 2 reserved r2 1 reserved r1 0 pcon r0
z8 family of microcontrollers user manual address space um001602-0904 26 the functions and applications of the control and peripheral re gisters are described in subsequent sections of this manual. pr ogram memory the ? rst 12 bytes of program memory are reserv ed for the interrupt v ec - tors , as sho wn in figure 8 . these locations contain six 16-bit v ectors that correspond to the six a v ailable interrupts. address 12 up to the maximum r om address consists of on-chip mask-programmable r om. see the product data sheet for the e xact program, data, re gister memory size, and address range a v ailable. at addresses outside the internal r om, the z8 ? cpu e x ecutes e xternal program memory fetches through port 0 and port 1 in address/data mode for de vices with port 0 and port 1 featured. oth - erwise, the program counter will continue to e x ecute nops up to address ffffh , roll o v er to 0000h , and continue to fetch e x ecutable code ( see figure 8 ) . the internal program memory is one-time programmable (o tp) or mask programmable dependent on the speci? c de vice. a r om pr otect featur e pr e vents dumping of the r om contents by inhibiting e xecution of the ldc, ldci, lde, and ldei instructions to pr o gr am memory in all modes. r om look-up tables cannot be used with this featur e . the r om protect option is mask-programmable, to be selected by the customer when the r om code is submitted. f or the o tp r om, the r om protect option is an o tp programming option.
z8 cpu user manual um001602-0904 address space 27 z8 exter nal memory th e z8 ? cpu , in some cases, has the capability to access e xternal pro - gram memory with the 16-bit program counter . t o access e xternal pro - figure 8. z8 pr ogram memor y map interrupt external on Cc hip 65535 rom and ram rom irq 5 4096 interrupt location of irq 0 irq 0 irq 1 irq 1 irq 2 irq 2 irq 3 irq 3 irq 4 irq 4 irq 5 4095 12 1 2 3 4 5 6 7 8 9 10 11 0 first byte of instruction executed after reset vector (lower byte) vector (upper byte)
z8 family of microcontrollers user manual address space um001602-0904 28 gram memory the z8 ? cpu of fers multiple x ed address/data lines (ad7C ad0) on port 1 and address lines (a15Ca8) on port 0. this feature only applies to de vices that of fer port 0 and port 1. the maximum e xternal address is ffff . this memory interf ace is supported by the control lines as (address strobe), ds (data strobe), and r/w (read/write). the ori - gin of the e xternal program memory starts after the last address of the internal r om. figure 9 s ho ws an e xample of e xternal program memory for the z8 ? cpu . external data memory th e z8 ? cpu , in some cases, can address up to 60 kb of e xternal data memory be ginning at location 4096. external data memory ( dm ) can be included with, or separated from, the e xternal program memory space. dm , an optional i/o function that can be programmed to appear on pin p34, is used to distinguish between data and program memory space. the state of the dm signal is controlled by the type of instruction being e x e - cuted. an ldc opcode references program memory ( dm inacti v e) , and an lde instruction references data memory ( dm acti v e lo w) . the user must con? gure port 3 mode re gister (p3m) bits d3 and d4 for this mode.
z8 cpu user manual um001602-0904 address space 29 *note: for additional information on using external memory, see chapter 10 of this manual. for exact memory addressing options available, see the device product specification. figure 9. external memor y map external 65535 memory 4096 not addressable 4095 0
z8 family of microcontrollers user manual address space um001602-0904 30 z8 stacks stack operations can occur in either the z8 ? s tandard re gister file or e xternal data memory . under softw are control, port 0C1 mode re gister ( f8h ) selects the stack location. only the general-purpose re gisters can be used for the stack when the internal stack is selected. the re gister pair feh and ffh form the 16-bit stack pointer (sp), that is used for all stack operations. the stack address is stored with the msb in feh and lsb in ffh ; see figure 10 . the stack address is decremented prior to a push operation and incre - mented after a pop operation. the stack address al w ays points to the data stored on the top of the stack. the z8 ? cpu stack is a return stack for call instructions and interrupts, as well as a data stack. during a call instruction, the contents of the pc are sa v ed on the stack. the pc is restored during a return instruction. interrupts cause the contents of the pc and flag re gisters to be sa v ed on the stack. the iret instruction restores them figure 11 . when the z8 ? cpu is con? gured for an internal stack (using the z8 ? standard re gister file), re gister ffh serv es as the stack pointer . the figure 10. stac k p ointer upper byte lower byte stack pointer high f fh stack pointer low f eh
z8 cpu user manual um001602-0904 address space 31 v alue in feh is ignored. feh can be used as a general-purpose re gister in this case only . an o v er? o w or under? o w can occur when the stack address is incre - mented or decremented during normal stack operations. the programmer must pre v ent this occurrence or unpredictable operation will result. figure 1 1. stack operations pcl top of stack stack contents pch pcl pch flags after an interrupt cycle stack contents after a call instruction top of stack
z8 family of microcontrollers user manual address space um001602-0904 32
z8 cpu user manual um001602-0904 clock 33 cloc k the z8 ? cpu d eri v es its timing from on-board clock circuitry connected to pins xt al1 and xt al2. the clock circuitry consists of an oscillator , a di vide-by-tw o shaping circuit, and a clock b uf fer . figure 12 i llustrates the clock circuitry . the oscillator s input is xt al1 and its output is xt al2. the clock can be dri v en by a crystal, a ceramic resonator , lc clock, rc, or an e xternal clock source. frequency control in some cases, the z8 ? cpu h as an epr om/o tp option or a mask r om option bit to bypass the di vide-by-tw o ? ip ? op in figure 12 . this feature is used in conjunction with the lo w emi option. when lo w emi is selected, the de vice output dri v e and oscillator dri v e is reduced to approx - imately 25 percent of the standard dri v e and the di vide-by-tw o ? ip ? op is bypassed such that the xt al clock frequenc y is equal to the internal sys - tem clock frequenc y . in this mode, the maximum frequenc y of the xt al clock is 4 mhz. please refer to speci? c product speci? cation for a v ailabil - ity of options and output dri v e characteristics. clock contr ol in some cases, the z8 ? cpu of fers softw are control of the internal system clock via programming re gister bits. the bits are located in the stop- mode reco v ery re gister in expanded re gister file bank f , re gister 0bh . figure 12. z8 ? cpu cloc k cir cuit 2 osc xtal2 internal buffer xtal1 clock
z8 family of microcontrollers user manual clock um001602-0904 34 this re gister selects the clock di vide v alue and determines the mode of stop-mode reco v ery (see figure 13 ). please refer to the speci? c product speci? cation for a v ailability of this feature/re gister . sclk tclk divide-by-16 select the d 0 bit of the smr controls a di vide-by-16 prescaler of sclk tclk. the purpose of this control is to selecti v ely reduce de vice po wer consumption during normal processor e x ecution (sclk control) and/or hal t mode (where tclk sources counter/timers and interrupt logic). external clock divide-by-two the d1 bit can eliminate the oscillator di vide-by-tw o circuitry . when this bit is 0, sclk (system clock) and tclk (t imer clock) are equal to the e xternal clock frequenc y di vided by tw o. the sclk tclk is equal to the e xternal clock frequenc y when this bit is set (d1 = 1). using this bit, together with d7 of pcon, further helps lo wer emi (d7 (pcon) = 0, d1 (smr) = 1). the def ault setting is 0. maximum frequenc y is 4 mhz with d1 = 1 ( see figure 14 ) . figure 13. stop-mode reco ver y register (w rite-only except d7, which is read-only) d7 d6 d5 d4 d3 d2 d1 d0 smr (f) ob sclk tclk d ivide by 16 0 off ** 1 on external clock divide mode by 2 0 = sclk tclk = xtal 2* 1 = sclk tclk = x tal * default setting after reset. **default setting after reset and stop-mode r ecovery.
z8 cpu user manual um001602-0904 clock 35 oscillator contr ol in some cases, the z8 ? cpu of fers softw are control of the oscillator to select lo w emi dri v e or standard dri v e. the selection is done by program - ming bit d7 of the port con? guration (pcon) re gister ( see figure 15 ) . the pcon re gister is located in expanded re gister file bank f , re gister 00h . figure 14. external cloc k cir cuit 2 osc external clock d1 (smr) 16 d0 (smr)
z8 family of microcontrollers user manual clock um001602-0904 36 a 1 in bit d7 con? gures the oscillator with standard dri v e, while a 0 con - ? gures the oscillator with lo w emi dri v e. this only af fects the dri v e capability of the oscillator and does not af fect the relationship of the xt al clock frequenc y to the internal system clock (sclk). oscillator operation the z8 ? cpu uses a pierce oscillator with an internal feedback ( see figure 16 ) . the adv antages of this circuit are lo w cost, lar ge output signal, lo w-po wer le v el in the crystal, stability with respect to v cc and tempera - ture, and lo w impedances (not disturbed by stray af fects). one dra wback is the requirement for high g ain in the ampli? er to com - pensate for feedback path losses. the oscillator ampli? es its o wn noise at start-up until it settles at the frequenc y that satis? es the g ain/phase requirements a x b = 1, where a = v 0 /v i is the g ain of the ampli? er and b = v i /v 0 is the g ain of the feedback element. the total phase shift around the loop is forced to zero (360 de grees). because vin must be in phase with itself, the ampli? er/in v erter pro vides 180 de gree phase shift and the feedback element is forced to pro vide the other 180 de grees of phase shift. r1 is a resisti v e component placed from output to input of the ampli? er . the purpose of this feedback is to bias the ampli? er in its linear re gion and to pro vide the start-up transition. figure 15. p or t con? guration register (w rite-only) d7 d6 d5 d4 d3 d2 d1 d0 pcon (fh) 00h low emi oscillator 0 low emi 1 standard
z8 cpu user manual um001602-0904 clock 37 capacitor c 2 combined with the ampli? er output resistance pro vides a small phase shift. it will also pro vide some attenuation of o v ertones. capacitor c 1 combined with the crystal resistance pro vides additional phase shift. c 1 and c 2 can af fect the start-up time if the y increase dramatically in size. as c 1 and c 2 increase, the start-up time increases until the oscillator reaches a point where it does not start up an y more. f or f ast and reliable oscillator start-up o v er the manuf acturing process range, zilog recommends that the load capacitors be sized as lo w as possible without resulting in o v ertone operation. layout t races connecting crystal, caps, and the z8 ? cpu oscillator pins should be as short and wide as possible. this reduces parasitic inductance and resistance. the components (caps, crystal, resistors) should be placed as close as possible to the oscillator pins of the z8 ? cpu . the traces from the oscillator pins of the ic and the ground side of the lead caps should be guarded from all other traces (clock, v cc , address/ figure 16. pier ce oscillator with internal feedbac k cir cuit xtal2 z8 cpu v ss xtal1 c1 c2 r i v 1 a v 0
z8 family of microcontrollers user manual clock um001602-0904 38 data lines, system ground) to reduce cross talk and noise injection. this is usually accomplished by k eeping other traces and system ground trace planes a w ay from the oscillator circuit and by placing a z8 ? cpu de vice v ss ground ring around the traces/components. the ground side of the oscillator lead caps should be connected to a single trace to the z8 ? cpu s v ss (gnd) pin. it should not be shared with an y other system ground trace or components e xcept at the z8 ? cpu s v ss pin. this is to pre v ent dif ferential system ground noise injection into the oscillator ( see figure 17 ) . indications of an unreliable design start-up time and output le v el a re tw o major indicators that are used in w orking designs to determine their reliability o v er full lot and tempera - ture v ariations. these tw o indicators are described belo w . start- up t im e . i f start - up time is e xcessi v e, or v aries widely from unit to unit, there is probably a g ain problem. c1/c2 must be reduced; the ampli - ? er g ain is not adequate at frequenc y , or crystal resistance i s too lar ge. output leve l . t he signal at the ampli? er output should swing from ground to v cc . this indicates there is adequate g ain in the ampli? er . as the oscillator starts up, the signal amplitude gro ws until clipping occurs, at which point the loop g ain is ef fecti v ely reduced to unity and constant oscillation is achie v ed. a signal of less than 2.5 v olts peak-to-peak is an indication that lo w g ain may be a problem. either c 1 or c 2 should be made smaller or a lo w-resistance crystal should be used. circuit board design rules the follo wing circuit board design rules are suggested: ? t o pre v ent induced noise the crystal and load capacitors should be ph ysically located as close to the z8 ? cpu as possible.
z8 cpu user manual um001602-0904 clock 39 ? signal lines should not run parallel to the clock oscillator inputs. in particular , the crystal input circuitry and the internal system clock output should be separated as much as possible. ? v cc po wer lines should be separated from the clock oscillator input circuitry . ? resisti vity between xt al1 or xt al2 and the other pins should be greater than 10 m ? .
z8 family of microcontrollers user manual clock um001602-0904 40 crystals and resonators crystals and ceramic resonators , sho wn in figure 18 s hould ha v e the c haracteristics listed in t able 11 to ensure proper oscillator operation. figure 17. circuit board design rules xtal2 v ss xtal1 board design example v ss 2 3 1 layout should avoid high lighted areas signal line 20 mm max z8 cpu z8 cpu z8 cpu c1 c2 3 2 clock generator circuit signals a b signal c (connection to system group must be avoided) (parallel traces must be avoided) (top view)
z8 cpu user manual um001602-0904 clock 41 depending on operation frequenc y , the oscillator may require the addition of capacitors c1 and c2 (sho wn in figure 18 ) . the capacitance v alues are dependent on the manuf acturer s crystal speci? cations. t able 1 1. crystal/resonator characteristics cr ystal cut : a t (cr ystal only) mod e: p ar allel, fu ndamental mo de cr ystal capacitance : < 7 pf load capacitance : 10 pf < cl < 220 pf , 15 typical resistance : 100 ? m ax figure 18. cr ystal/ceramic resonator oscillator xtal2 z8 cpu v ss xtal1 c1 c2 r f r d
z8 family of microcontrollers user manual clock um001602-0904 42 in most cases, the r d is 0 ? and r f is in? nite. it is determined and speci - ? ed by the crystal/ceramic resonator manuf acturer . the r d can be increased to decrease the amount of dri v e from the oscillator output to the crystal. it can also be used as an adjustment to a v oid clipping of the oscil - lator signal to reduce noise. the r f can be used to impro v e the start-up of the crystal/ceramic resonator . the z8 ? oscillator already has an internal shunt resistor in parallel to the crystal/ceramic resonator . figure 19. lc cloc k figure 20. external cloc k xtal2 z8 cpu v ss xtal1 c1 c2 l xtal2 z8 cpu v ss xtal1
z8 cpu user manual um001602-0904 clock 43 in figures 18 through 20 , zilog recommends that the user connect the load capacitor ground trace directly to the v ss (gnd) pin of the z8 ? cpu to ensure that no system noise is injected into the z8 ? clock. this trace should not be shared with an y other components e xcept at the v ss pin of the z8 ? cpu . in some cases, the z8 ? cpu s xt al1 pin also functions as one of the epr om high-v oltage mode programming pins or as a special f actory test pin. in this case, applying 2 v abo v e v cc on the xt al1 pin will cause the de vice to enter one of these modes. because this pin accepts high v olt - ages to enter these respecti v e modes, the standard input protection diode to v cc is not on xt al1. zilog recommends that in applications where the z8 ? cpu is e xposed to much system noise, a diode from xt al1 to v cc be used to pre v ent accidental enabling of these modes. this diode will not af fect the crystal/ceramic resonator operation. please note that a parallel resonant crystal or resonator data sheet will specify a load capacitor v alue that is the series combination of c 1 and c 2 , including all parasitics (pcb and holder). lc oscillator the z8 ? cpu oscillator can use a lc netw ork to generate a xt al clock ( see figure 19 ) . the frequenc y stays stable o v er v cc and temperature. the oscillation fre - quenc y is determined by the equation. where l is the total inductance including parasitics and c t is the total series capacitance including the parasitics. simple series capacitance is calculated using the follo wing equation: frequency = 1 2 (lc t ) 1/2
z8 family of microcontrollers user manual clock um001602-0904 44 sample calculation of capacitance c 1 and c 2 for 5.83 mhz frequenc y and inductance v alue of 27 h. rc oscillator in some cases, the z8 ? cpu features an rc oscillator option. please refer to the speci? c product speci? cation for a v ailability . the rc oscillator requires a resistor across xt al1 and xt al2. an additional load capaci - tor is required from the xt al1 input to v ss pin ( see figure 21 ) . 1 = 1 + 1 c t c 1 c 2 if c 1 = c 2 1 = 2 c t = c 1 c 1 = 2ct 5.83 (10 6 ) = 1 2 [2.7 (10 C6 ) c t ] 1/2 c t = 2 7.6 pf thus c 1 = 55.2 pf and c 2 = 55.2 pf .
z8 cpu user manual um001602-0904 clock 45 figure 21. rc cloc k xtal2 z8 cpu v ss xtal1 c1 r
z8 family of microcontrollers user manual clock um001602-0904 46
z8 cpu user manual um001602-0904 reset 47 reset this section describes the z8 ? cpu reset conditions, reset timing, and re gister initialization procedures. reset is generated by po wer -on reset (por), reset pin, w atchCdog t imer (wdt), and stop-mode reco v ery . a system reset o v errides all other operating conditions and puts the z8 ? cpu into a kno wn state. t o initialize the chip s internal logic, the reset input must be held lo w for at least 21 scp or 5 xt al clock c ycles. the control re gister and ports are reset to their def ault conditions after a por, a reset from the reset pin, or w atchCdog t imer time-out while in r un mode and hal t mode. the control re gisters and ports are not reset to their def ault conditions after stop- mode reco v ery and wdt time-out while in st op mode. while reset pin is lo w , as is output at the internal clock rate, ds is forced lo w , and r/ w remains high. the program counter is loaded with 000ch . i/o ports and control re gisters are con? gured to their def ault reset state. resetting the z8 ? cpu does not af fect the contents of the general-pur - pose re gisters. reset pin, inter nal por operation in some cases, the z8 ? cpu hardw are reset pin initializes the control and peripheral re gisters, as sho wn in t ables 12 through 15 . speci? c reset v alues are sho wn by 1 or 0, while bits whose states are unkno wn are indi - cated by the letter u. t ables 12 through 15 s ho w the reset conditions for the z 8 cpu . the re gister ? le reset state is de vice dependent. please refer to the selected de vice product speci? cations for re gister a v ailability and reset state. note:
z8 family of microcontrollers user manual reset um001602-0904 48 t able 12. s ample control and peripheral register reset v alues (erf bank 0) registe r ( hex) registe r n ame bits comments 7 6 5 4 3 2 1 0 f0 serial i/o u u u u u u u u f1 t imer mode 0 0 0 0 0 0 0 0 counter/t imers st opped . f2 counter/t imer1 u u u u u u u u f3 t1 prescaler u u u u u u 0 0 single- pa ss co unt mo de, ex ternal cl ock so urce . f4 counter/t imer0 u u u u u u u u f5 t0 prescaler u u u u u u u 0 single-pass count mode. f6 port 2 mode 1 1 1 1 1 1 1 1 all in puts . f7 port 3 mode 0 0 0 0 0 0 0 0 port 2 open-drain, p33C p30 input, p37Cp34 output . f8 port 0C1 mode 0 1 0 0 1 1 0 1 internal stack, normal memory t iming . f9 interrupt priority u u u u u u u u f a interrupt request 0 0 0 0 0 0 0 0 all interrupts cleared . fb interrupt mask 0 u u u u u u u interrupts disabled . fc flags u u u u u u u u fd register pointer 0 0 0 0 0 0 0 0 fe stack pointer (high) u u u u u u u u ff stack pointer (low) u u u u u u u u
z8 cpu user manual um001602-0904 reset 49 program e x ecution starts 5 to 10 clock c ycles after internal reset has returned high. the initial instruction fetch is from location 000ch . figure 22 illustrates r eset timing. after a reset, the ? rst routine e x ecuted should be one that initializes the control re gisters to the required system con? guration. the reset pin is the input of a schmitt-triggered circuit. resetting the z8 ? cpu will initialize port and control re gisters to their def ault states. t o form the internal reset line, the output of the trigger is synchronized with the internal clock. the clock must therefore be running for reset to function. it requires 4 internal system clocks after reset is detected for the z8 ? cpu to reset the internal circuitry . an internal pull-up, combined with an e xternal capacitor of 1 uf, pro vides enough time to properly reset the z8 ? cpu ( see figure 23 ) . in some cases, the z8 ? cpu has an internal por timer circuit that holds the z8 ? cpu in reset mode for a duration figure 22. reset timing first machine cycle t1 clock reset as ds r/w first instruction fetch hold low for 4 sclk periods (minimum) sclk
z8 family of microcontrollers user manual reset um001602-0904 50 (t por ) before releasing the de vice out of reset. on these z8 de vices, the internally generated reset dri v es the reset pin lo w for the por time. an y de vices dri ving the reset line must be open-drained in order to a v oid dam - age from possible con? ict during reset conditions. this reset time allo ws the on-board clock oscillator to stabilize. t o a v oid asynchronous and noisy reset problems, the z8 ? cpu is equipped with a reset ? lter of four e xternal clocks (4tpc). if the e xternal reset signal is less than 4tpc in duration, no reset occurs. on the ? fth clock after the reset is detected, an internal rst signal is latched and held for an internal re gister count of 18 e xternal clocks, or for the duration of the e xternal reset, whiche v er is longer . during the reset c ycle, ds is held acti v e lo w while as c ycles at a rate of the internal system clock. program e x ecution be gins at location 000ch , 5-10 tpc c ycles after reset is released. f or the internal po wer -on reset, the reset output time is speci - ? ed as t por . please refer to speci? c product speci? cations for actual v al - ues. figure 23. example of external p o wer -on reset cir cuit 1 f +5v 100 k ? r eset 1k to 200 k ? 10 v
z8 cpu user manual um001602-0904 reset 51 t able 13. expanded register file bank 0 reset v alues at reset registe r ( hex) registe r n ame bits comments 7 6 5 4 3 2 1 0 00 port 0 u u u u u u u u input mode, output set to pushCpull . 01 port 1 u u u u u u u u input mode, output set to pushCpull . 02 port 2 u u u u u u u u input mode, output set to open drain . 03 port 3 1 1 1 1 u u u u standard digital i nput and output z86l7x family device port p34-p37 = 0 (except z86l70/71/75) all other z8 = 1 . 04Cef general -p urpos e r egister s 0 4 hC e f h u u u u u u u u undefined . t able 14. sample expanded register file bank c reset v alues registe r ( hex) registe r n ame bits comments 7 6 5 4 3 2 1 0 00 spi compare (scomp) 0 0 0 0 0 0 0 0 01 receive buf fer (rxbuf) u u u u u u u u 02 spi control (scon) u u u u 0 0 0 0
z8 family of microcontrollers user manual reset um001602-0904 52 t able 15. sample expanded register file bank f reset v alues registe r ( hex) registe r n ame bits comments 7 6 5 4 3 2 1 0 00 port configuration (pcon) 1 1 1 1 1 1 1 0 comparator outputs disabled on port 3 . port 0 and 1 output is pushCpull . port 0, 1, 2, 3, and oscillator with standard output drive . 0b stop-mode r ecovery (smr) 0 0 1 0 0 0 0 0 clock divide by 16 of f . xt al divide by 2 . por and /o r external reset . stop delay on . stop recovery level is low , st op flag is por . 0f w atchCdog t imer mode (wdtmr) u u u 0 1 1 0 1 512 tpc for wdt time out, wdt runs during st op .
z8 cpu user manual um001602-0904 reset 53 figure 24. example of z8 reset with reset pin, wdt , smr, and por 256 tpc 256 512 1024 4096 wdt/por counter chain por tpc tpc tpc tpc + - m wdt tap select clear 18 clock reset reset clk generator 4 clock filter ck clr rc osc. u x internal reset 2.6v operating voltage det. r eset from stop mode recovery source stop delay select (smr) w dt . vdd xtal wdt select (wdtmr) clk source select (wdtmr) 2.6v ref
z8 family of microcontrollers user manual reset um001602-0904 54 figure 25. example of z8 reset with wdt , smr, and por 5ms por 5ms 15ms 25ms 100ms wdt/por counter chain clk + - m wdt tap select 4 clock filter clr internal rc osc. u x 2v operating voltage det. from stop mode recovery source stop delay select (smr) wdt . v d d xtal wdt select (wdtmr) clk source select (wdtmr) v l v internal reset clear clk 18 clock reset generator reset
z8 cpu user manual um001602-0904 watchCdog timer 55 w atchCdog timer the w atch-dog t imer (wdt) is a retriggerable one-shot timer that resets the z8 ? cpu if it reaches its terminal count. when operating in the r un or hal t modes, a wdt reset is functionally equi v alent to a hardw are por reset. the wdt is initially enabled by e x ecuting the wdt instruc - tion and refreshed on subsequent e x ecutions of the wdt instruction. the wdt cannot be disabled after it has been initially enabled. permanently enabled wdts are al w ays enabled and the wdt instruction is used to refresh it. the wdt circuit is dri v en by an on-board rc oscillator or e xternal oscillator from the xt al1 pin. the por clock source is selected with bit 4 of the w atchCdog t imer mode re gister (wdtmr). in some cases, a z8 that of fers the wdt b ut does not ha v e a wdtmr re gister , has a ? x ed wdt time-out and uses the on board rc oscillator as the only clock source. please refer to speci? c product speci? cations for selectabil - ity of time-out, wdt during hal t and st op modes, source of wdt clock, and a v ailability of the permanently-on wdt option. ex ecution of the wdt instruction af fects the z (zero), s (sign), and v (o v er? o w) ? ags.
z8 family of microcontrollers user manual watchCdog timer um001602-0904 56 the wdtmr re gister is accessible only during the ? rst 60 processor c ycles from the e x ecution of the ? rst instruction after po wer -on reset, w atchCdog reset or a stop-mode reco v ery . after this point, the re gister cannot be modi? ed by an y means, intentional or otherwise. the wdtmr is a write-only re gister . w dtmr is located in expanded re gister file bank f , re gister 0fh . this re gister s c ontrol bits are described on the ne xt tw o pages. figure 26. example of z8 w atc hCdog timer mode register (w rite- only) d7 d6 d5 d4 d3 d2 d1 d0 wdtmr (f) 0f int 00 5 128 01** 10 256 10 20 512 11 80 2048 wdt rc sys tap* osc clk wdt during stop 0 off 1 on * wdt during halt 0 off 1 on * xtal1/int rc 0 on-board rc * 1 xtal reserved (must be 0) select for wdt * must be 0 for z86c03 reserved (must be 0) ** default setting after reset
z8 cpu user manual um001602-0904 watchCdog timer 57 wdt t ime select . bits d1 and d0 control a tap circuit that determines the time-out period. t able 16 s ho ws the dif ferent v alues that can be obtained. the def ault v alue of d1 and d0 are 0 and 1, respecti v ely . wdt during hal t . the d2 bit determines whether or not the wdt is acti v e during hal t mode. a 1 indicates acti v e during hal t . the def ault is 1. a wdt time out during hal t mode will reset control re gister ports to their def ault reset conditions. wdt during st op . the d3 bit determines whether or not the wdt is acti v e during st op mode. because xt al clock is stopped during st op mode, unless as speci? ed belo w , the on-board rc must be selected as the clock source to the por counter . a 1 indicates acti v e during st op . the def ault is 1. if bits d3 and d4 are both set to 1, the wdt only , is dri v en by the e xternal clock during st op mode. this feature mak es it possible to w ak e up from st op mode from an internal source. please refer to spe - ci? c product speci? cations for conditions of control and port re gisters when the z8 ? cpu comes out of st op mode. a wdt time out during st op mode will not reset all control re gisters. the reset conditions of the ports from st op mode due to wdt time out is the same as if reco v ered using an y of the other st op mode sources. t able 16. t ime-out period of the wdt time-out of t ypica l t ime-out o f i nternal rc osc system c lock d1 d0 0 0 5 ms min 256 tpc 0 1 15 ms min 512 tpc 1 0 25 ms min 1024 tpc 1 1 100 ms min 4096 tpc *notes: the values given are for v cc = 5.0v. see the device product specification for exact wdtmr time out select options available. 1. tpc = xtal clock cycle 2. the default on reset is, d0 = 1 and d1 = 0 .
z8 family of microcontrollers user manual watchCdog timer um001602-0904 58 clock sour ce for wdt . the d4 bit determines which oscillator source is used to clock the internal por and wdt counter chain. if the bit is a 1, the internal rc oscillator is bypassed and the por and wdt clock source is dri v en from the e xternal pin, xt al1. the def ault con? guration of this bit is 0, which selects the internal rc oscillator . bits 5, 6, and 7 . these bits are reserv ed. v cc v oltage comparator . an on-board v oltage comparator checks that v cc is at the required le v el to insure correct operation of the de vice. reset is globally dri v en if v cc is belo w the speci? ed v oltage. this feature is a v ailable in select r om z8 de vices. see the de vice product speci? cation for feature a v ailability and operating range. p o wer-on-reset a timer circuit clock ed by a dedicated on-board rc oscillator is used for the po wer -on reset (por) timer function, t por . this por time allo ws v cc and the oscillator circuit to stabilize before instruction e x ecution be gins. the por timer circuit is a one-shot timer triggered by one of three condi - tions: ? po wer f ail to po wer ok status (cold start) ? stop-mode reco v ery (if bit 5 of smr = 1) ? wdt time-out the por time is speci? ed as t por . on z8 de vices that feature a stop- mode reco v ery re gister (smr), bit 5 selects whether the por timer is used after stop-mode reco v ery or by-passed. if bit d5 = 1 then the por timer is used. if bit 5 = 0 then the por timer is by-passed. in this case, the stop-mode reco v ery source must be held in the reco v ery state for 5 t p c or 5 crystal clocks to pass the reset signal internally . this option is used
z8 cpu user manual um001602-0904 watchCdog timer 59 when the clock is pro vided with an rc/lc clock. see the de vice product speci? cation for timing details. por (cold start) will al w ays reset the z8 ? cpu c ontrol and port re gisters to their def ault condition. if a z8 has a smr re gister , the w arm start bit will be reset to a 0 to indicate por. figure 27. example of z8 with simple smr and por int osc chip por reset p27 (stop mode) (cold start) vbo wdt delay line t por ms 18 clk reset filter xtal osc
z8 family of microcontrollers user manual watchCdog timer um001602-0904 60
z8 cpu user manual um001602-0904 i/o ports 61 i/o p orts th e z8 ? cpu features u p to 32 lines dedicated to input and output. these lines are grouped into four 8-bit ports kno wn as port 0, port 1, port 2, and port 3. port 0 is nibble programmable as input, output, or address. port 1 is byte con? gurable as input, output, or address/data. port 2 is bit pro - grammable as either inputs or outputs, with or without handshak e and spi. port 3 can be programmed to pro vide timing, serial and parallel input/output, or comparator input/output. all ports ha v e pushCpull cmos outputs. in addition, the pushCpull out - puts of port 2 can be turned of f for open-drain operation. mode registers each port has an associated mode re gister that determines the port s functions and allo ws dynamic change in port functions during program e x ecution. port and mode re gisters are mapped into the standard re gis - ter file as sho wn in figure 28 .
z8 family of microcontrollers user manual i/o ports um001602-0904 62 because of their close association, port and mode re gisters are treated lik e an y other general-purpose re gister . there are no special instructions for port manipulation. an y instruction which addresses a re gister can address the ports. data can be directly accessed in the port re gister , with no e xtra mo v es. input and output registers each bit of ports 0, 1, and 2, ha v e an input re gister , an output re gister , associated b uf fer , and control logic. because there are separate input and output re gisters associated with each port, writing to bits de? ned as inputs stores the data in the output re gister . this data cannot be read as long as the bits are de? ned as inputs. ho we v er , if the bits are recon? gured as out - puts, the data stored in the output re gister is re? ected on the output pins figure 28. i/o p or ts and mode register s register hex port 3 m ode port 2 mode identifier f8h f7h f6h p01m p3m p2m port 3 port 0 C1 m ode port 2 port 1 port 0 03h 02h 01h 00h p3 p2 p1 p0
z8 cpu user manual um001602-0904 i/o ports 63 and can then be read. this mechanism allo ws the user to initialize the out - puts prior to dri ving their loads ( see figure 29 ) . because port inputs are asynchronous to the z8 ? cpu internal clock, a read operation could occur during an input transition. in this case, the logic le v el might be uncertain (some where between a logic 1 and 0). t o eliminate this meta-stable condition, the z8 ? cpu latches the input data tw o clock periods prior to the e x ecution of the current instruction. the input re gister uses these tw o clock periods to stabilize to a le gitimate logic le v el before the instruction reads the data. the follo wing sections describe the generic function of the z8 ? cpu ports. an y additional features of the ports such as spi, c/t , and stop- mode reco v ery are co v ered in their o wn section. p ort 0 this section deals with only the i/o operation of port 0. the port's e xter - nal memory interf ace operation is co v ered later in this manual. figure 29 s ho ws a block diagram of port 0. this diagram also applies to ports 1 and 2. note:
z8 family of microcontrollers user manual i/o ports um001602-0904 64 figure 29. ports 0, 1, 2 generic block diagram handshake logic internal timing handshake selected rdy/ d av d av /rdy port i/o lines input buffer input register handshake logic output buffer output register output enable internal bus write port read port e 8 8 8 8 8 8 8
z8 cpu user manual um001602-0904 i/o ports 65 general i/o mode port 0 can be an 8-bit, bidirectional, cmos or ttl compatible i/o port. these eight i/o lines can be con? gured under softw are control as a nibble i/o port (p03 Cp0 0 input/output and p07 Cp0 4 input/output), or as an address port for interf acing e xternal memory . the input b uf fers can be schmitt-triggered, le v el shifted, or a single-trip point b uf fer and can be nibble programmed. either nibble output can be globally programmed as pushCpull or open-drain. lo w emi output b uf fers in some cases can be globally programmed by the softw are a s an o tp program option o r as a r om mask option. in such cases, the z8 ? mcu features autolatche s that are hardwired to the inputs. please refer to the s peci? c z8 mcu p roduct speci? cation f or the e xact input/output b uf fer f eatures that are a v ailable ( see figures 30 and 31 ) .
z8 family of microcontrollers user manual i/o ports um001602-0904 66 figure 30. port 0 configuration with open-drain capability , autolatch, and schmitt-t rigger oen port 1 (i/o or ad15Cad08) handshake controls d av0 and rdy0 4 z8 (p32 and p35) pin out in 2.3v hysteresis open-drain 1.5 r 500 k ? autolatch 4
z8 cpu user manual um001602-0904 i/o ports 67 read/write operations in the nibble i/0 mode, port 0 is accessed as general-purpose re gister p0 ( 00h ) with erf bank set to 0. the port is written by specifying p0 as an instruction's destination re gister . writing to the port causes data to be stored in the port's output re gister . the port is read by specifying p0 as the source re gister of an instruction. when an output nibble is read, data on the e xternal pins is returned. under normal loading conditions this is equi v alent to reading the output re gister . ho we v er , for port 0 outputs de? ned as openCdrain, the data returned is the v alue forced on the output by the e xternal system. this may not be the same as the data in the output re gister . reading a nibble de? ned as input also returns data on the e xternal pins. ho we v er , input bits figure 31. port 0 configuration with ttl level shifter oen pin out in ttl level shifter
z8 family of microcontrollers user manual i/o ports um001602-0904 68 under handshak e control return data latched into the input re gister via the input strobe. the port 0C1 mode resist or bit s d1 C d0 and d7 C d6 ar e used to con? gure port 0 nibbles. the lo wer nibble (p00Cp03) can be de? ned as inputs by setting bits d1 to 0 and d0 to 1, or as outputs by setting both d1 and d0 to 0. lik e wise, the upper nibble (p04Cp07) can be de? ned as inputs by setting bits d7 to 0 and d6 to 1, or as outputs by setting both d6 and d7 to 0 (see figure 32 ). handshake operation when used as an i/0 port, port 0 can be placed under handshak e control by programming the port 3 mode re gister bit d2 to 1. in this con? gura - tion, handshak e control lines are d a v0 (p32) and rd y0 (p35) when port 0 is an input port, or rd y0 (p32) and d a v0 (p35) when port 0 is an out - put port (se e figure 33 ). handshak e direction is determin ed by the con? guration (input or output) assigned to the port 0 upper nibble, p04Cp07. the lo wer nibble must ha v e the same i/0 con? guration as the upper nibble to be under handshak e con - trol. figure 30 i llustrates the port 0 upper and lo wer nibbles and the asso - ciated handshak e lines of port 3. p ort 1 this section deals only with the i/0 operation. the port's e xternal memory interf ace operation is discussed later in this manual. figure 29 s ho ws a block diagram of port 1. general i/o mode port 1 can be an 8-bit, bidirectional, cmos or ttl compatible port with multiple x ed address (a7Ca0) and data (d7Cd0) ports. these eight i/o lines can be byte programmed as inputs or outputs or can be con? gured under softw are control as an address/data port for interf acing to e xternal
z8 cpu user manual um001602-0904 i/o ports 69 memory . the input b uf fers can be schmitt-triggered, le v el- shifted, or a single-point b uf fer . in some cases, the output b uf fers can be globally pro - grammed as either pushCpull or open-drain. lo w-emi output b uf fers can be globally programmed by softw are, as an o tp program option, or as a r om mask option. in some cases, the z8 ? mcu c an ha v e autolatche s hardwired to the inputs. please refer to speci? c product speci? cations for e xact input/output b uf fer -type features a v ailable ( figures 32 and 33 ) . figure 32. p or t 0 i/o operation figure 33. p or t 0 handshake operation d7 d6 d1 d0 (write-only) 01 = input 1x = a 8Ca11 p0 0Cp03 mode 00 = output port 0C1 m ode register (p01m) register f8h (p01m) p0 4Cp07 mode 00 = output 01 = input 1x = a 12Ca15 d2 (write-only) 0 p3 2 = input p3 5 = output port 3 mode register (p3m) register f7h 1 p3 2 = dav0/rdy0 p3 5 = rdy0/dav0
z8 family of microcontrollers user manual i/o ports um001602-0904 70 figure 34. port 1 configuration with open-drain capability , autolatch, and schmitt-t rigger oen port 1 (i/o or ad7Cad0) handshake controls d av1 and rdy1 8 z8 (p33 and p34) pin out in 2.3v hysteresis open-drain 1.5 r 500 k ? autolatch
z8 cpu user manual um001602-0904 i/o ports 71 read/write operations in byte input or byte output mode, the port is accessed as general-purpose re gister p1 ( 01h ). the port is written by specifying p1 as an instruction's figure 35. port 1 configuration with ttl level shifter oen port 1 (i/o or ad7Cad0) 8 z8 (p33 and p34) pin out in ttl level shifter handshake controls da v1 and rdy1
z8 family of microcontrollers user manual i/o ports um001602-0904 72 destination re gister . writing to the port causes data to be stored in the port's output re gister . the port is read by specifying p1 as the source re gister of an instruction. when an output is read, data on the e xternal pins is returned. under nor - mal loading conditions, this is equi v alent to reading the output re gister . ho we v er , if port 1 outputs are de? ned as open-drain, the data returned is the v alue forced on the output by the e xternal system. this may not be the same as the data in the output re gister . when port 1 is de? ned as an input, reading also returns data on the e xternal pins. ho we v er , inputs under handshak e control return data latched into the input re gister via the input strobe. using the port 0C1 mode re gis ter , port 1 is con? gured as an output port by setting bits d4 and d3 to 0, or as an input port by setting d4 to 0 and d3 to 1 ( see figure 36 ) . figure 36. p or t 1 i/o operation d4 d3 (f8, write-only) port 0C1 mode register r248 p01m 01 = byte output 10 = ad 0-ad7 00 = byte output p1 0Cp13 mode as , ds , r /w, 11 = high impedance ad 0 Ca d7, a 8Ca11, a12Ca15
z8 cpu user manual um001602-0904 i/o ports 73 handshake operations when used as an i/o port, port 1 can be placed under handshak e control by programming the port 3 mode re gister bits d4 and d3 both to 1. in this con? guration, handshak e control lines are d a v1 (p33) and rd y1 (p34) when port 1 is an input port, or rd y1 (p33) and d a v1 (p34) when port 1 is an output port. see figures 37 and 39 . handshak e direction is determined by the con? guration (input and output) assigned to port 1. f or e xample, if port 1 is an output port then handshak e is de? ned as output. p ort 2 port 2 is a general-purpose port. figure 29 s ho ws a block diagram of port 2. each of its lines can be independently programmed as input or output via the port 2 mode re gister ( f6h ) as seen in figure 38 . a bit set to a 1 in p2m con? gures the corresponding bit in port 2 as an input, while a bit set to 0 con? gures an output line. figure 37. handshake operation d4 d3 (f7, write-only) 00 p33 = input p34 = output 01 p33 = input p34 = dm port 3 mode register r247 p3m 10 p33 = input p34 = dm 11 p33 = da v1 /rdy1 p34 = rdy1/ da v1
z8 family of microcontrollers user manual i/o ports um001602-0904 74 general port i/o port 2 can be an 8-bit, bidirectional, cmos- or ttl- compatible i/o port. these eight i/o lines can be con? gured under softw are control to be an input or output, independently . input b uf fers can be schmitt-triggered, le v el-shifted, or a single trip point b uf fer and may contain autolatche s. bits programmed as outputs may be globally programmed as either pushC pull or open-drain. lo w-emi output b uf fers can be globally programmed by the softw are, an o tp program option, or as a r om mask option. in addition, when the spi is featured and enabled, p20 functions as data-in (di), and p27 functions as data-out (do). please refer to speci? c product speci? cations for e xact input/output b uf fer type features a v ailable. see figures 39 through 41 . figure 38. p or t 2 i/o mode con? guration d7 d6 d5 d4 d3 d2 d1 d0 (write-only) 1 = input port 2 mode 0 = output port 2 mode register (p2m) register f6h
z8 cpu user manual um001602-0904 i/o ports 75 figure 39. port 2 configuration with open-drain capability , autolatch, and schmitt-t rigger p21 Cp2 6 oe pin p21 Cp2 6 out p21 Cp2 6 in 2.3v hysteresis @ v cc = 5.0v open-drain 1.5 r 500 k ? autolatch p21 Cp2 6
z8 family of microcontrollers user manual i/o ports um001602-0904 76 figure 40. port 2 configuration with ttl level shifter oen pin out in ttl level shifter open-drain
z8 cpu user manual um001602-0904 i/o ports 77 figure 41. port 2 configuration with open-drain capability , autolatch, schmitt-t rigger and spi p27 out pin spi active p27 in 0 soi d0 enable open-drain r 500 k ? autolatch p27 p20 oe pin p20 out p20 in open-drain r 500 k ? autolatch p20 spi en spi do p27 oe spi spi do spi standard standard 1 p27 out *spi must be enabled with d0 d2 scon or spi di
z8 family of microcontrollers user manual i/o ports um001602-0904 78 read/write operations port 2 is accessed as general-purpose re gister p2 ( 02h ). port 2 is written by specifying p2 as an instruction s destination re gister . writing to port 2 causes data to be stored in the output re gister of port 2, and re? ected e xternally on an y bit con? gured as an output. port 2 is read by specifying p2 as the source re gister of an instruction. when an output bit is read, data on the e xternal pin is returned. under normal loading conditions, this is equi v alent to reading the output re gister . ho we v er , if a bit of port 2 is de? ned as an open-drain output, the data returned is the v alue forced on the output pin by the e xternal system. this may not be the same as the data in the output re gister . reading input bits of port 2 also returns data on the e xternal pins. ho we v er , inputs under handshak e control return data latched into the input re gister via the input strobe. handshake operation port 2 can be placed under handshak e control by programming bit 6 in the port 3 mode re gister ( see figure 42 ) . in this con? guration, port 3 lines p31 and p36 are used as the handshak e control lines d a v2 a nd rd y2 for input handshak e, or rd y2 and d a v2 for output handshak e. handshak e direction is determined by the con? guration (input or output) assigned to bit 7 of port 2. only those bits with the same con? guration as p27 will be under handshak e control. figure 43 i llustrates the bit lines of port 2 and the associated handshak e lines of port 3.
z8 cpu user manual um001602-0904 i/o ports 79 figure 42. p or t 2 handshake con? guration figure 43. p or t 2 handshaking d7 d6 d5 d4 d3 d2 d1 d0 (write-only) port 3 mode register register f7h 1 p31 = da v2 /rdy2 p36 = rdy2/ da v2 0 p31 = input (t in ) p36 = output (t out ) port 2 handshaking handshake controls da v2 and rdy2 (p3 1 and p36) p2 7 port 2 (i/o) p2 0
z8 family of microcontrollers user manual i/o ports um001602-0904 80 p ort 3 general port i/o port 3 dif fers structurally from port 0, 1, and 2. port 3 lines are ? x ed as four inputs (p33Cp30) and four outputs (p37Cp34) port 3 does not ha v e an input and output re gister for each bit. instead, all of the i nput lines ha v e one input re gister , and all of the o utput lines ha v e an output re gister . port 3 can be a cmos- or ttl- compatible i/o port. under softw are control, the lines can be con? gured as special control lines for handshak e, com - parator inputs, spi control, e xternal memory status, or i/o lines for the on-board serial and timer f acilities. figure 44 i s a generic block diagram of port 3. the inputs can be schmitt-triggered, le v el-shifted, or single-trip point b uf fered. in some cases, the z8 ? mcu m ay ha v e autolatche s hardwired on certain port 3 inputs and lo w-emi capabilities on the outputs. please refer to speci? c product speci? cations for e xact input/output b uf fer type features. please refer to the section on counter/timers, stop-mode reco v - ery , serial i/o, comparators, and interrupts for more information on the relationships of port 3 to that feature.
z8 cpu user manual um001602-0904 i/o ports 81 figure 44. port 3 block diagram input buffer input register output buffer output register output register write port read port 4 4 4 4 4 4 4 4 internal bus from timer, handshake logic, or serial i/o to interrupt timer, handshake logic, or serial i/o port output lines p3 4 Cp3 7 port input lines p3 0 Cp3 3 read port input buffer output buffer output register output buffer data return
z8 family of microcontrollers user manual i/o ports um001602-0904 82
z8 cpu user manual um001602-0904 i/o ports 83 figure 45. port 3 configuration with comparator , autolatch, and schmitt-t rigger p31 (an1) r247 = p3m + - irq2, t in , p31 data latch p30 + - 1 = analog 0 = digital d1 r 500 k ? autolatch port 3 (i/o or control) p30 data latch irq3 z8 p34 p35 p37 p36 p30 p31 p32 p33 irq0, p32 data latch irq1, p33 data latch p32 (an2) p33 (ref) from stop-mode recovery source dig. an.
z8 family of microcontrollers user manual i/o ports um001602-0904 84 figure 46. port 3 configuration with comparator pin p37 0 p34, p37 standard output 1 p34, p37 comparator output d0 p37 out pcon p32 ref (p33) + - pin p34 p37 out p32 ref (p33) + -
z8 cpu user manual um001602-0904 i/o ports 85
z8 family of microcontrollers user manual i/o ports um001602-0904 86 figure 47. port 3 configuration with spi and comparator outputs spi mstr pin p31 + spi en p34 sk in spi mstr pin p35 spi en ref ss 0 p34, p35 standard output 1 p34, p35 comparator output d0 p34 out pcon p31 ref + - p34 out - spi en sk out mux
z8 cpu user manual um001602-0904 i/o ports 87 read/write operations port 3 is accessed as a general-purpose re gister p3 ( 03h ). port 3 is writ - ten by specifying p3 as an instruction s destination re gister . ho we v er , port 3 outputs cannot be written to if the y are used for special functions. when writing to port 3, data is stored in the output re gister . port 3 is read by specifying p3 as the source re gister of an instruction. when reading from port 3, the data returned is both the data on the input pins and in the output re gister . figure 48. port 3 configuration with ttl level shifter and autolatch pin pin out r 500 k ? autolatch in ttl level shifter port 3 output configuration port 3 input configuration
z8 family of microcontrollers user manual i/o ports um001602-0904 88 special functions special functions for port 3 are de? ned by programming the port 3 mode re gister . by writing 0s in bit 6 through bit 1, lines p37Cp30 are con? g - ured as input/output pairs ( see figure 49 ) . t able 17 s ho ws a v ailable func - tions for port 3. the special functions indicated in the ? gure are discussed in detail in their corresponding sections in this manual. port 3 input lines p33Cp30 al w ays function as interrupt requests re g ard - less of the con? guration speci? ed in the port 3 mode re gister . figure 49. p or t 3 mode register con? guration d7 d6 d5 d4 d3 d2 d1 d0 (write-only) 0 p31, p32 digital mode 1 p31, p32 analog mode 0 p32 = input p35 = output 0 port 2 open-drain 1 port 2 pushCpull 00 p33 = input p34 = output 01 p33 = input p34 = d m port 3 mode register register f7h 10 p33 = input p34 = dm 0 p31 = input p36 = output 0 p30 = input p37 = output 1 p30 = serial in p37 = serial out 0 party on 1 party off
z8 cpu user manual um001602-0904 i/o ports 89 t able 17. port 3 line functions function line signal inputs p30 input p31 input p32 input p33 input outputs p34 output p35 output p36 output p37 output port 0 handshake input p32 da v0 /rdy0 port 1 handshake input p33 da v1 /rdy1 port 2 handshake input p31 da v2 /rdy2 port 0 handshake output p35 rdy0/ da v0 port 1 handshake output p34 rdy1/ da v1 port 2 handshake output p36 rdy2/ da v2 analog comparator input p31 an1 p32 an2 p33 ref analog comparator output p34 an1-out p35 an2-out p37 an2-out
z8 family of microcontrollers user manual i/o ports um001602-0904 90 p ort handshake when ports 0, 1, and 2 are con? gured for handshak e operation, a pair of lines from port 3 are used for handshak e controls. the handshak e controls are interlock ed to properly time asynchronous data transfers between the z8 ? and a peripheral. one control line ( d a v ) functions as a strobe from the sender to indicate to the recei v er that data is a v ailable. the second control line (rd y) ackno wledges receipt of the sender s data, and indi - cates when the recei v er is ready to accept another data transfer . in input mode, data is latched into the port s input re gister by the ? rst d a v signal, and is protected from being o v erwritten if additional pulses occur on the d a v line. this o v erwrite protection is maintained until the port data is read. in o utput mode, data written to the port is not protected and can be o v erwritten by the z8 ? cpu during the handshak e sequence. interrupt requests p30 irq3 p31 irq2 p32 irq0 p33 irq1 serial input (uar t) p30 di serial output (uar t) p37 do spi slave select p35 ss spi clock p34 sk counter/t imer p31 t in p36 t out external memory status p34 dm t able 17. port 3 line functions (continued) function line signal
z8 cpu user manual um001602-0904 i/o ports 91 t o a v oid losing data, the softw are must not o v erwrite the port until the corresponding interrupt request indicates that the e xternal de vice has latched the data. the softw are can al w ays read port 3 output and input handshak e lines, b ut cannot write to the output handshak e line. the follo wing is the recommended setup sequence when con? guring a port for handshak e operation for the ? rst time after a reset: ? load p01m or p2m to con? gure the port for input/output ? load p3 to set the output handshak e bit to a logic 1 ? load p3m to select handshak e mo de for the port once a data transfer be gins, the con? guration of the handshak e lines should not be changed until the handshak e is completed. figures 50 and 51 s ho w detailed operation for the handshak e sequence.
z8 family of microcontrollers user manual i/o ports um001602-0904 92 figure 50. z8 input handshake valid data (input to z8) state 1. 2 1 3 4 5 d av (output from z8) rdy (input to z8) data on port port 3 output is high, indicating that the i/o device is ready to accept data. state 2. the i/o device puts data on the port and then activates the da v input. this causes the data to be latched . state 3. the z8 ? cpu forces the ready (rdy) output low, signaling to the i/o device that the data has been latched. state 4. the i/o device returns the da v line high in response to rdy going low. state 5. the z8 ? cpu rr software must respond to the interrupt request and read the contents of the port in order for t into the port input register and generates an interrupt request. handshake sequence to be completed. the rdy line goes high if and only if the port has been read and da v is high. this returns the interface to its initial state.
z8 cpu user manual um001602-0904 i/o ports 93 in applications requiring a strobed signal instead of the interlock ed hand - shak e, the z8 ? cpu c an satisfy this requirement as follo ws: ? in the strobed input mode, data can be latched in the port input re gis - ter using the d a v input. the data transfer rate must allo w enough time for the softw are to read the port before strobing in the ne xt char - acter . the rd y output is ignored. ? in the strobed output mode, the rd y input should be tied to the d a v output. figure 51. z8 output handshake valid data (input to z8) state 1. 2 1 3 4 5 rdy (output from z8) da v (output from z8) data on port rdy input is high indicating that the i/o device is ready to accept data. state 2. the z8 ? cpu writes to the port register to initiate a data transfer. writing to the port outputs new data and forces da v low if and only if rdy is high. state 3. the i/o device forces rdy low after latching the data. rdy low causes an interrupt request to be generat e the z8 ? cpu can write new data responses to rdy going low; however, the data is not output until state 5 state 4. the da v output from the z8 ? cpu is driven high in response to rdy going low. state 5. the da v goes high, the i/o device is free to raise rdy high thus returning the interface to its initial state.
z8 family of microcontrollers user manual i/o ports um001602-0904 94 figures 52 and 53 i llustrate the strobed handshak e connections. i/o p ort reset conditions full reset after a hardw are reset, w atchCdog t imer (wdt) reset, or a po wer -on reset (por), port mode re gisters p01m, p2m, and p3m are set as figure 52. output str obed handshake on p or t 2 figure 53. input str obed handshake on p or t 2 p3 6 z8 p2 0 Cp 27 p3 1 i/o device da v rdy z8 p2 0 Cp 27 p3 1 i/o device da v
z8 cpu user manual um001602-0904 i/o ports 95 sho wn in figures 54 through 56 . port 2 is con? gured for input operation on all bits and is set for open-drain ( see figure 55 ) . if push-pull outputs are required for port 2 outputs, remember to con? gure them using p3m. please note that a wdt time-out from stop-mode reco v ery does not do a full reset. certain re gisters that are not reset after stop-mode reco v ery will not be reset. f or the condition of the ports after stop-mode reco v ery , please refer to speci? c de vice product speci? cations. in some cases, an z8 ? mcu fea - tures t he p01m, p2m, and p3m control re gister set back to the def ault condition after reset while others do not. all special i/o functions of port 3 are inacti v e, with p33Cp30 set as inputs and p37Cp34 set as outputs ( see figure 56 ) . because the types and amounts of i/o v ary greatly among the z8 ? cpu f amily de vices, the user is advised to re vie w the selected de vice's product speci? cations for the re gister def ault state after reset.
z8 family of microcontrollers user manual i/o ports um001602-0904 96 figure 54. port 0/1 reset 0 1 0 0 1 1 0 1 (write-only) 01 = input 1x = a 8Ca11 stack selection 0 = external p0 0Cp03 mode 00 = output port 0C1 mode register (p01m) register f8h 01 = byte output 1 = internal external memory timing normal = 0 extended = 1 p0 4Cp07 mode output = 00 input = 01 a 12Ca15 = 1x 10 = ad 0Cad7 00 = byte output p 10Cp17 mode a 8Ca15, as , ds , r /w 11 = high impedance ad 0Cad7,
z8 cpu user manual um001602-0904 i/o ports 97 figure 55. p or t 2 reset 1 1 1 1 1 1 1 1 (write-only) 1 = input port 2 mode 0 = output port 2 mode register (p2m) register f6h
z8 family of microcontrollers user manual i/o ports um001602-0904 98 analog comparators select z8 de vices include tw o independent on-chip analog comparators. see the de vice product speci? cation for feature a v ailability and use. port 3, pins p31 and p32 each ha v e a comparator front end. the comparator reference v oltage, pin p33, is common to both comparators. in analog mode, the p31 and p32 are the positi v e inputs to the comparators and p33 is the reference v oltage supplied to both comparators. in digital mode, pin p33 can be used as a p33 re gister input or irq1 source. p34, p35, or p37 figure 56. p or t 3 mode reset 0 0 0 0 0 0 0 0 (write-only) 0 p31, p32 digital mode 1 p31, p32 analog mode 0 p32 = input p35 = output 1 p32 = da v0 /rdy0 p35 = rdy0/ da v0 0 port 2 open-drain 1 port 2 pushCpull 00 p33 = input p34 = output 01 p33 = input p34 = dm port 3 mode register (p3m) register f7h 10 p33 = input p34 = dm 11 p33 = da v1 /rdy1 p34 = rdy1/ da v1 0 p31 = input p36 = output 1 p32 = da v2/ rdy2 p36 = rdy2/ da v2 0 p30 = input p37 = output 1 p30 = serial in p37 = serial out 0 parity off 1 parity on
z8 cpu user manual um001602-0904 i/o ports 99 may output the comparator outputs by softw are-programming the pcon re gister bit d0 to 1. comparator description t w o on-board comparators can process analog signals on p31 and p32 with reference to the v oltage on p33. the analog function is enabled by programming the port 3 mode re gister (p3m bit 1). f or interrupt func - tions during analog mode, p31 and p32 can be programmable as rising, f alling, or both edge triggered interrupts (irq re gister bits 6 and bit 7). p33 cannot generate an e xternal interrupt while in this mode. p33 can only generate interrupts in di gital mo de. port 3 inputs must be in digital mode if port 3 is a stop-mode reco v ery source. the analog comparator is disabled in st op mode. p31 can be used as t in in an alog or di gital mo des, b ut it must be refer - enced to p33, when in analog mode. figure 57. p or t 3 input analog selection d1 (write-only) 0 = digital mode p31, p32, p33 1 = analog mode p31, p32, p33 port 3 mode register (p3m) register f7h
z8 family of microcontrollers user manual i/o ports um001602-0904 100 figure 58. p or t 3 comparator output selection d0 (write-only) 0 = p34, p35, or p37 standard outputs 1 = p34, p35, or p37 comparator outputs port configuration register (pcon) register 00h erf bank f
z8 cpu user manual um001602-0904 i/o ports 101 figure 59. port configuration of comparator inputs on p31, p32, and p33 p31 (an1) r247 = p3m + - irq2, t in , p31 data latch p30 + - 1 = analog 0 = digital d1 r 500 k ? autolatch port 3 (i/o or control) p30 data latch irq3 z8 p34 p35 p37 p36 p30 p31 p32 p33 irq0, p32 data latch irq1, p33 data latch p32 (an2) p33 (ref) from stop-mode recovery source dig. an.
z8 family of microcontrollers user manual i/o ports um001602-0904 102 comparator programming example of enabling analog comparator mode. x = an y bi nary nu mber example of enabling analog comparator output. figure 60. port 3 configuration ld p3m, #xxxx xx1x b pin p37 0 p34, p37 standard output 1 p34, p37 comparator output d0 p37 out pcon p32 ref (p33) + - pin p34 p34 out p31 ref (p33) + -
z8 cpu user manual um001602-0904 i/o ports 103 comparator operation after enabling the analog comparator mode, p33 becomes a common reference input for both comparators. the p33 (ref) is hard wired to the reference inputs to both comparators and cannot be separated. p31 and p32 are al w ays connected to the positi v e inputs to the comparators. p31 is the positi v e input to comparator an1 while p32 is the positi v e input to comparator an2. the outputs to comparators an1 and an2 are an1-out and an2-out, respecti v ely . the comparator output re? ects the relationship between the positi v e input to the reference input. exampl e i f the v oltage on an1 is higher than the v oltage on ref then an1-out will be at a high state. if v oltage on an2 is lo wer than the v oltage on ref then an2-out will be at a lo w state. in this e xample, when the port 3 re gister is read, bits d1 = 1 and d2 = 0. if the comparator outputs are enabled to come out on p34 and p37, then p34 = 1 and p37 = 0. please note that the pre vious data stored in p34 and p37 is not disturbed. once the comparator outputs are de-selected the stored v alues in the p34 and p37 re gister bits will be re? ected on these pins ag ain. ld rp , #%0fh ;sets register pointer to ;w or king register g roup 0 ;and expanded register ;file bank f . ld r0, #xxxx xxx1 b ;enab les compar ator ;outputs using pco n ;register prog r amming .
z8 family of microcontrollers user manual i/o ports um001602-0904 104 interrupts in the e xample from section 5.8.3, p32 (an2) will generate an interrupt based on the result of the comparison being lo w and the interrupt request re gister (irq fah ) ha ving bits d7 = 0 and d6 = 0. if irq d7 = 1 and d6 = 0 then both p31 and p32 w ould generate interrupts. comparator definitions v icr the usable v oltage range for both positi v e inputs and the reference input is called the common mode v oltage range (v icr ). the comparator is not guaranteed to w ork if the inputs are outside of the v icr range. v offset the absolute v alue of the v oltage between the positi v e input and the refer - ence input required to mak e the comparator output v oltage switch is the input of fset v oltage (v offset ). if an1 is 3.000v and ref is 3.001v when the comparator output switches states then the v of fset = 1mv . i io f or cmos v oltage comparator inputs, the input of fset current (i io ) is the leakage current of the cmos input g ate. run mode p33 is not a v ailable as an interrupt input during analog mode. p31 and p32 are v alid interrupt inputs in conjunction with p33 (ref) when in ana - log mode. p31 can still be used as t in when a nalog mode is selected. if comparator outputs are required to be outputted on the port 3 outputs, please refer to speci? c products speci? cation for priority of mixing when other special features are sharing those same port 3 pins.
z8 cpu user manual um001602-0904 i/o ports 105 halt mode the analog comparators are functional during hal t mode i f an alog mo de has been enabled. p31 and p32, in conjunction with p33 (ref) will be able to generate interrupts. only p33 cannot generate an interrupt because the p33 input goes directly to the ref input of the comparators and is disconnected from the interrupt sensing circuits. stop mode the analog comparators are disabled during st op mode s o it does not use an y current at that time. if p31, p32, or p33 are used as a source for stop-mode reco v ery , the port 3 digital mode m ust be selected by setting bit d1 = 0 in the port 3 mode re gister . otherwise in st op mode, the p31, p32, and p33 cannot be sensed. if an alog mo de w as selected when entering st op mo de, it will still be enabled after a v alid smr triggered reset. open-drain con? guration all z8 ? mcu s can con? gure port 2 to pro vide open-drain outputs by pro - gramming the port 3 mode re gister (p3m) bit d0 = 0. other z8 ? mcu s feature a port con? guration re gister (pcon) for which p ort 0 and port 1 can be con? gured to pro vide open-drain outputs. figure 61. p or t 2 con? guration d7 d6 d5 d4 d3 d2 d1 d0 (write-only) 0 = pull-ups active port 2 configuration 1 = pull-ups open-drain port 3 mode register register f7h
z8 family of microcontrollers user manual i/o ports um001602-0904 106 the pcon re gister is located in expanded re gister file (erf) bank f , re gister 00h . see figure 62 . port 1 open-drain . port 1, d1 can be con? gured as open-drain by reset - ting this bit (d1 = 0) or con? gured as pushCpull acti v e by setting this bit (d1 = 1). the def ault v alue is 1. port 0 open drain . port 0, d2 can be con? gured as open-drain by reset - ting this bit (d2 = 0) or con? gured as pushCpull acti v e by setting this bit (d2 = 1). the def ault v alue is 1. figure 62. p or t con? guration register (write-onl y) d7 d6 d5 d4 d3 d2 d1 d0 pcon (fh) 00h 0 port 1 open drain 1 port 1 pushCpull active * 0 p34, p37 standard output* 1 p34, p37 comparator output comparator output port 3 low emi oscillator 0 port 0 open drain 1 port 0 pushCpull active * 0 port 0 low emi 1 port 0 standard * 0 port 1 low emi 1 port 1 standard * 0 port 2 low emi 1 port 2 standard * 0 low emi 1 standard * 0 port 3 low emi 1 port 3 standard * * default setting after reset
z8 cpu user manual um001602-0904 i/o ports 107 lo w emi emission some z8 ? mcu s can be programmed to operate in a lo w emi emission mode using the port con? guration re gister (pcon). the pcon re gister allo ws the oscillator and all i/o ports to be programmed in the lo w-emi mode independently . other z8 ? mcu s may of fer a r om mask or o tp programming option to con? gure the z8 ? mcu po rts and oscillator glo - bally to a lo w-emi mode (where the xt al frequenc y is set equal to the internal system clock frequenc y . use of the lo w emi feature results in: ? the output pre-dri v ers sle w rate reduced to 10 ns (typical) ? lo w emi output dri v ers ha v e resistance of 200 ? (typical) ? lo w emi oscillator ? all output dri v ers are approximately 25 percent of the standard dri v e ? internal sclk tclk = xt al operation limited to a maximum of 4 mhzC250 ns c ycle time, when lo w emi oscillator is selected and system clock (sclk = xt al, smr re g. bit d1 = 1) f or z8 ? mcu s ha ving the pcon re gister feature, the follo wing bits con - trol the lo w emi options . low emi port 0 . port 0, d3 can be con? gured as a lo w emi port by resetting this bit (d3 = 0) or con? gured as a standard port by setting this bit (d3 = 1). the def ault v alue is 1. low emi port 1 . port 1, d4 can be con? gured as a lo w emi port by resetting this bit (d4 = 0) or con? gured as a standard port by setting this bit (d4 = 1). the def ault v alue is 1. low emi port 2 . port 2, d5 can be con? gured as a lo w emi port by resetting this bit (d5 = 0) or con? gured as a standard port by setting this bit (d5 = 1). the def ault v alue is 1.
z8 family of microcontrollers user manual i/o ports um001602-0904 108 low emi port 3 . port 3, d6 can be con? gured as a lo w emi port by resetting this bit (d6 = 0) or con? gured as a standard port by setting this bit (d6 = 1). the def ault v alue is 1. low emi osc . this d7 bit of the pcon re gister controls the lo w emi oscillator . a 1 in this location con? gures the oscillator with standard dri v e, while a 0 con? gures the oscillator with lo w noise dri v e. the lo w- emi mode will reduce the dri v e of the oscillator (osc). the def ault v alue is 1. xt al 2 mode is not af fected by this bit. the maximum e xternal clock frequenc y is 4 mhz when running in the lo w emi oscillator mode. please refer to the selected de vice product speci? cation for a v ailability of the lo w emi feature and programming options. input pr otection all cmos r om z8 ? mcu s ha v e i/o pins with diode input protection. there is a diode from the i/o pad to v cc and to v ss . see figure 63 .
z8 cpu user manual um001602-0904 i/o ports 109 on cmos o tp epr om z8 ? mcu s , the port 3 inputs p31, p32, p33 and the xt al 1 pin ha v e only the input protection diode from pad to v ss . see figure 64 . figure 63. diode input pr otection pin v cc v ss
z8 family of microcontrollers user manual i/o ports um001602-0904 110 the high-side input protection diodes were remo v ed on these pins to allo w the application of +12.5v during the v arious o tp programming modes. f or better noise immunity in applications that are e xposed to system emi, a clamping diode to v cc from these pins may be required to pre v ent entering the o tp programming mode or to pre v ent high v oltage from damaging these pins. z8 cmos a utolatches i/o port bits that are con? gurable as inputs are protected ag ainst open cir - cuit conditions using autolatche s. an autolatch i s a circuit which, in the e v ent of an open circuit condition, latches the input at a v alid cmos le v el. this inhibits the tendenc y of the input transistors to self-bias in the forw ard acti v e re gion, thus dra wing e xcessi v e supply current. a simpli? ed schematic of the cmos z8 i/o circuit is sho wn in figure 65 . figure 64. o tp diode input pr otection pin v ss
z8 cpu user manual um001602-0904 i/o ports 111 the operation of the autolatch c ircuit is straight-forw ard. assume the input pad is latched at +5v (logic 1). the in v erter g1 in v erts the bit, turn - ing the p-channel fet on and the n-channel fet off . the output of the circuit is ef fecti v ely shorted to v dd , returning +5v to the input. if the pad is then disconnected from the +5v source, the autolatch w ill hold the input at the pre vious state. if the de vice is po wered up with the input ? oat - figure 65. simplified cmos z8 i/o circuit open-drain pin v dd oe data out data in autolatch g1 n p v dd n p
z8 family of microcontrollers user manual i/o ports um001602-0904 112 ing, the state of the autolatch w ill be at either supply , b ut which state is unpredictable. there are four operating conditions which will acti v ate the autolatche s. the ? rst, which occurs when the input pin is ph ysically disconnected from an y source, is the most ob vious. the second occurs when the input is connected to the output of a de vice with tri-state capability . the autolatch w ill also acti v ate when the input v oltage at the pin is not within 200 micro v olts or so of either supply rail. in this case, the circuit will dra w current, which is not signi? cant compared to the i cc o perating current of the de vice, b ut will increase i cc2 st op mode c urrent of the de vice dramatically . the fourth condition occurs when the i/o bit is con? gured as an output. referring to the output section of figure 65 , there are tw o w ays of tri-stat - ing the port pin. the ? rst is by con? guring the port as an input, which dis - ables the oe signal turning both transistors of f. the second can be achie v ed in output mode by writing a 1 to the output port, then acti v ating the open drain mode. both transistors are ag ain of f, and the port bit is in a high impedance state. the autolatche s then pull the input section to w ard v dd . autolatch m odel the autolatch s equi v alent circuit is sho wn in figure 66 . when the input is high, the circuit consists of a resistance rp from v dd (the p-channel transistor in its on state) and a much greater resistance rh to g nd . cur - rent i ao ? o ws from v dd to the output. when the input is lo w , the circuit may be modeled as a resistance rp from g nd (the n-channel transistor in the on state) and a much greater resistance rh to v dd . current i ao no w ? o ws from the input to ground. the autolatch i s characterized with respect to i ao , so the equi v alent resistance rp is calculated according to r p = (v dd Cv in )/i ao . the w orst case equi v alent resistance rp (min) may be calculated at the w orst case input v oltage, v i = v ih (min).
z8 cpu user manual um001602-0904 i/o ports 113 design considerations f or circuits in which the autolatch i s acti v e, consideration should be gi v en to the loading constraints of the autolatche s. f or e xample, with weak v al - ues of v in , close to v ih (min) or v il (max), pullup or pull-do wn resis - tances must be calculated using ref = r/rp. f or best case st op mode operation, the inputs should be within 200 mv of the supply rails. in output mode, if a port bit is forced into a tri-state condition, the auto - latche s will force the pad to v dd . if there is an e xternal pulldo wn resistor on the pin, the v oltage at the pin may not switch to gnd due to the auto - latch. as sho wn in figure 67 , the equi v alent resistance of the autolatch a nd the e xternal pulldo wn form a v oltage di vider , and if the e xternal resis - tor is lar ge, the v oltage de v eloped across it will e xceed v il (max). f or w orst case . v il (max > v dd [r ext (r ext + r p )] r ext (max) = [(v il (max) v dd ) r p ] [1(v il (max) v dd )] for v dd = 5.0 v and i ao = 5 a, v i h (max) = 0.8 v : r ext (max) = (0.16 1m) (10.16) = 190 k?. figure 66. autolatch e quivalent circuit v dd data in pin logic 1 a0 pin v dd r p r h r h r p data in logic 0 a0
z8 family of microcontrollers user manual i/o ports um001602-0904 114 rp increases rapidly with v dd , so increased v dd will relax the require - ment on re xt. in summary , the cmos z8 autolatch i nhibits e xcessi v e current drain in z8 de vices by latching an open input to either v dd or gnd. the ef fect of the autolatch o n the i/o characteristics of the de vice may be modeled by a current i ao and a resistor rp, whose v alue is v dd /i ao . figure 67. eff ect of pulldo wn resistor s on a utolatc he s v lo v ih (min.) r p r ext
z8 cpu user manual um001602-0904 counters and timers 115 counters and t imers th e z8 ? cpu pro vides up to tw o 8-bit counter/timers, t0 and t1, each dri v en by its o wn 6-bit prescaler , pre0 and pre1 ( see figure 68 ) . both counter/timers are independent of the processor instruction sequence, that relie v es softw are from time-critical operations such as interv al timing or e v ent counting. some mcus of fer clock scaling using the smr re gister . see the de vice product speci? cation for clock a v ailable options. the fol - lo wing description is typical. each counter/timer operates in either single-p ass or continuous mode. at the end-of-count, counting either stops or the initial v alue is reloaded and counting continues. under softw are control, ne w v alues are loaded imme - diately or when the end-of-count is reached. softw are also controls the counting mode, ho w a counter/timer is started or stopped, and its use of i/ o lines. both the counter and prescaler re gisters can be altered while the counter/timer is running.
z8 family of microcontrollers user manual counters and timers um001602-0904 116 counter/timers 0 and 1 are dri v en by a timer clock generated by di viding the internal clock by four . the di vide-by-four stage, the 6-bit prescaler , and the 8-bit counter/timer form a synchronous 16-bit di vide chain. counter/timer 1 can also be dri v en by a e xternal input (t in ) using p31. port 3 line p36 can serv e as a timer output (t out ) through which t0, t1, or the internal clock can be output. the timer output will toggle at the end-of-count. the counter/timer , prescaler , and associated mode re gisters are mapped into the re gister ? le as sho wn in figure 69 . this allo ws the softw are to figure 68. counter/timer bloc k dia gram 2 osc d1 (smr) 16 d0 (smr) clock 4 logic internal clock external clock internal clock gated clock triggered clock t in p31 4 6-bit down counter 8-bit down counter pre1 initial value register t1 initial value register t1 current value register write read write write read write 6-bit down counter 8-bit down counter pre0 initial value register t0 initial value register t0 current value register 2 internal data bus internal data bus t out irq 4 p36 irq 5
z8 cpu user manual um001602-0904 counters and timers 117 treat the counter/timers as general-purpose re gisters, and eliminates the requirement for special instructions. pr escalers and counter/timers the prescalers, pre0 ( f5h ) and pre1 ( f3h ), each consist of an 8-bit re g - ister and a 6-bit do wn-counter as sho wn in figure 68 . the prescaler re gis - ters are write-only re gisters. reading the prescalers returns the v alue ffh . figures 70 and 71 s ho w the prescaler re gisters. the six most signi? cant bits (d2 Cd 7) of pre0 or pre1 hold the prescal - ers count modulo, a v alue from 1 to 64 decimal. the prescaler re gisters also contain control bits that specify t0 and t1 counting modes. these bits also indicate whether the clock source for t 1 is internal or e xternal. these control bits will be discussed in detail throughout this chapter . the counter/timer re gisters, t0 ( f4h ) and t1 ( f2h ), each consist of an 8- bit do wn-counter , a write-only re gister that holds the initial count v alue, and a read-only re gister that holds the current count v alue ( figure 68 ) . the initial v alue can range from 1 to 256 decimal ( 01h , 02h ,.., 00h ). figure 72 i llustrates the counter/timer re gisters.
z8 family of microcontrollers user manual counters and timers um001602-0904 118 figure 69. counter/timer register map figure 70. prescaler 0 register hex identifiers t0 prescaler f7 timer/counter0 port 3 mode t1 prescaler time/counter1 timer mode f5 f4 f3 f2 f1 dec 247 245 244 243 242 241 d7 d6 d5 d4 d3 d2 d1 d0 (%f5; write-only) 1 = t 0 modulo-n count mode 0 = t 0 single pass prescaler 0 register r245 pre0 01-00 hex) prescaler modulo (range: 1-64 decimal reserved (must be 0)
z8 cpu user manual um001602-0904 counters and timers 119 figure 71. prescaler 1 register figure 72. counter/timer 0 and 1 register s u u u u u u 0 0 (%f3; write-only) 1 = t 1 modulo-n count mode 0 = t 1 single pass prescaler 1 register r243 pre1 01-00 hex) prescaler modulo (range: 1-64 decimal clock source 0 = t 1 external (t in ) 1 = t 1 internal d7 d6 d5 d4 d3 d2 d1 d0 (%f4; write/read only) current value when read initial value when written (range 1-256 decimal, 01-00 hex) counter/timer 0 register r244 t0 (%f2; write/read only) counter/timer 1 register r242 t1
z8 family of microcontrollers user manual counters and timers um001602-0904 120 counter/t imer operation under softw are control, counter/timers are started and stopped via the t imer mode re gister (tmr, f1h ) bits d0 Cd 3 ( see figure 73 ) . each counter/timer is associated with a load bit and an enable count bit. load and enable count bits setting the load bit (d0 for t0 and d2 for t1) tra nsfers the initial v alue in the prescaler and the counter/timer re gisters into their respecti v e do wn- counters. the ne xt internal clock resets bit s d0 and d2 to 0, readying the load bit for the ne xt load operation. ne w v alues may be loaded into the do wn-counters at an y time. if the counter/timer is running, it continues to do so and starts the count o v er with the ne w v alue. therefore, the load bit actually functions as a softw are re-trigger . the counter timers remain at rest as long as the enable count bits are 0. t o enable counting, the enable count bit (d 1 for t0 and d 3 for t1) must figure 73. timer mode register d3 d2 d1 d0 (% f1; read/write) 0 = disable t 0 count 0 = no function 1 = load t 0 timer mode register r241 tmr 1 = enable t 0 count 0 = no function 1 = load t 1 0 = disable t 1 count 1 = enable t 1 count
z8 cpu user manual um001602-0904 counters and timers 121 be set to 1. counting actually starts when the enable count bit is written by an instruction. the ? rst decrement occurs four internal clock periods after the enable count bit has been set. if t1 is con? gured to use an e xter - nal clock, the ? rst decrement be gins on the ne xt clock period. the load and enable count bits can be set at the same time. f or e xample, using the instruction: or tmr,#03h sets both d0 and d1 of the tmr. this loads the initial v alues of pre0 and t0 into their respecti v e counters and starts the count after the m2t2 machine state after the operand is fetched ( see figure 74 ) . figure 74. star ting the count d0 (% f5; wr ite-only) count mode prescaler 0 register r245 pre0 (% f3; wr ite-only) prescaler 1 register r243 pre1 0 = t 1 single p ass 1 = t 1 modulo-n
z8 family of microcontrollers user manual counters and timers um001602-0904 122 prescaler operations during counting, the programmed clock source dri v es the 6-bit prescaler counter . the counter is counted do wn from the v alue speci? ed by bits of the corresponding prescaler re gister , pre0 (bit 7 to bit 2) or pre1 (bit 7 to bit 2 ; see figures 70 and 71 ) . when the prescaler counter reaches its end-of-count, the initial v alue is reloaded and counting continues. the prescaler ne v er actually reaches 0. f or e xample, if the prescaler is set to di vide-by-three, the count sequence is: 3 C2C1C3C2C1C3C2C1C3... each time the prescaler reaches its end of count a carry is generated, that allo ws the counter/t imer to decrement by one on the ne xt timer clock input. when the counter/t imer and the prescaler both reach the end-of- count, an interrupt request is generated (irq4 for t0, irq5 for t1). depending on the counting mode selected, the counter/t imer will either come to rest with its v alue at 00h (single-p ass mode) or the initial v alue will be automatically reloaded and counting will continue (continuous mode). the counting modes are controlled by bit 0 of pre0 and bit 0 of pre1 (see figure 75 ) . a 0, written to this bit con? gures the counter for figure 75. counting modes t1 t2 t3 t1 t2 t3 t1 t2 t3 t1 t2 t3 tmr is written, counter/timer first decrement occurs four clock periods later is loaded #03h is fetched m3 m1 m2 mn
z8 cpu user manual um001602-0904 counters and timers 123 single-pass counting mode, while a 1 written to this bit con? gures the counter for continuous mode. the counter/t imer can be stopped at an y time by setting the enable count bit to 0, and restarted by setting it back to 1. the counter/t imer will continue its count v alue at the time it w as stopped. the current v alue in the counter/t imer can be read at an y time without af fecting the count - ing operation. the prescaler re gisters are write-only and cannot be read. ne w initial v alues can be written to the prescaler or the counter/t imer re gisters at an y time. these v alues will be transferred to their respecti v e do wn counters on the ne xt load operation. if the counter/t imer mode is continuous, the ne xt load occurs on the timer clock follo wing an end-of- count. ne w initial v alues should be written before the load operation, because the prescalers al w ays ef fecti v ely operate in continuous count mode. the time interv al (i) until end-of-count, is gi v en by the equation: i = t x p x v in which t = four times the internal clock period. the internal clock frequenc y def aults to the e xternal clock source (xt al, ceramic resonator , and others) di vided by 2. some z8 microcontrollers allo w this di visor to be changed via the stop-mode reco v ery re gister . see the product data sheet for a v ailable clock di visor options. t is equal to eight di vided-by-xt al frequenc y of the e xternal clock source for t1 (e xternal clock mode only). p = the prescaler v alue (1C63) for t 0 and t 1 . the minimum prescaler count of 1 is achie v ed by loading 000001xx . the maximum prescaler count of 63 is achie v ed by loading 111111xx . v = the counter/t imer v alue (1C256) note:
z8 family of microcontrollers user manual counters and timers um001602-0904 124 minimum duration is achie v ed by loading 01h (1 prescaler output count), maximum duration is achie v ed by loading 00h (256 prescaler outputs counts). the prescaler and counter/timer are true di vide-by-n counters. t out modes the t imer mode re gister tmr ( f1h ; see figure 76 ) , is used in conjunc - tion with the port 3 mode re gister p3m ( f7h ; see figure 77 ) to con? gure p36 for t out operation for t0 and t1. in order for t out to function, p36 must be de? ned as an output line by setting p3m bit 5 to 0. output is con - trolled by one of the counter/timers (t0 or t1) or the internal clock. figure 76. timer mode register (t out operation) d7 d6 d3 d0 (read/write) 0 = no function 1 = load t 0 timer mode register (tmr) register f1hr t out modes: 0 = disable t 1 count 1 = enable t 1 count t out off = 00 t 0 out = 01 t 1 out = 10 internal clock out = 11
z8 cpu user manual um001602-0904 counters and timers 125 the counter/timer to be output is selected by tmr bit 7 and bit 6. t0 is selected to dri v e the t out line by setting bit 7 to 0 and bit 6 to 1. lik e - wise, t1 is selected by setting bit 7 and bit 6 to 1 and 0, respecti v ely . the counter/timer t out mode is turned of f by setting tmr bit and bit 6 both to 0, freeing p36 to be a data output line. t out is initialized to a logic 1 whene v er the tmr load bit (bit 0 for t0 or bit 1 for t2) is set to 1. the t out con? guration timer load, and t imer enable count bits for the counter/timer dri ving the t out pin can be set at the same time. f or e xample, using the instruction: or tmr,#43h ? con? gures t0 to dri v e the t out pin (p36) ? sets the p36 t out pin to a logic 1 le v el ? loads the initial pre0 and t0 le v els into their respecti v e counters and starts the counter after the m2t2 machine state after the operand is fetched at end-of-count, the interrupt request line (irq4 or irq5), clocks a tog - gle ? ip-? op. the output of this ? ip-? op dri v es the t out line, p36. in all cases, when the selected counter/timer reaches its end-of-count, t out toggles to its opposite state ( see figure 78 ) . if, for e xample, the counter/ figure 77. p or t 3 mode register (t out operation) d7 d6 d5 d4 d3 d2 d1 d0 (write-only) port 3 mode register (p3m) register f7h 0 p31 = input (t in ) p36 = output (t out ) 1 p31 = dav2 /rdy2 p36 = rdy2/ dav2
z8 family of microcontrollers user manual counters and timers um001602-0904 126 timer is in continuous counting mode, t out will ha v e a 50 percent duty c ycle output. this duty c ycle can easily be controlled by v arying the ini - tial v alues after each end-of-count. the internal clock can be selected as output instead of t0 or t1 by setting tmr bit 7 and bit 6 both to 1. the internal clock (xt al frequenc y 2 ) is then directly output on p36 ( see figure 79 ) . while programmed as t out , p36 cannot be modi? ed by a write to port re gister p3. ho we v er , the z8 ? softw are can e xamine the p36 current out - put by reading the port re gister . figure 78. t0 and t1 output thr ough t out 2 p3 6 t out tmr d 7Cd6 = 01 irq 4 (t0 end-of-count) irq 5 (t1 end-of-count) tmr d 7Cd6 = 10
z8 cpu user manual um001602-0904 counters and timers 127 t in modes the t imer mode re gister tmr ( f1h ; see figure 80 ) is used in conjunc - tion with the prescaler re gister pre1 ( f3h ; see figure 81 ) to con? gure p31 as t in . t in is used in conjunction with t1 in one of four modes: ? external clock input ? gated internal clock ? t riggered internal clock ? retriggerable internal clock the t in mode is restricted for use with timer 1 only . t o enable the t in mode selected (via tmr bits 4- 5), bit 1 of pre1 must be set to 0. the counter/timer clock source must be con? gured for e xternal by setting the pre1 re gister bit 2 to 1. the t imer mode re gister bit 5 and bit 4 can then be used to select the appropriate t in operation. figure 79. internal cloc k output thr ough t out osc 2 p3 6 t out internal tmr d 6 clock tmr d 7
z8 family of microcontrollers user manual counters and timers um001602-0904 128 f or t1 to start counting as a result of a t in input, the enable count bit (bit 3 in tmr) must be set to 1. when using t in as an e xternal clock or a g ate input, the initial v alues must be loaded into the do wn counters by set - ting the load bit (bit 2 in tmr) to a 1 before counting be gins. in the descriptions of t in that follo w , it is assumed the programmer has per - formed these operations. initial v alues are automatically loaded in t rigger and retrigger modes so softw are loading is unnecessary . figure 80. timer mode register (t in operation) figure 81. prescaler 1 register (t in operation) d5 d4 (read/write) timer mode register (tmr) register f1h (retriggerable) (non-retriggerable) trigger input = 10 t in = modes: external clock input = 00 gate input = 01 trigger input = 11 d7 d6 d5 d4 d3 d2 d1 d0 (write-only) 1 = t 1 internal disable t in mode clock source 0 = t 1 external enable t in mode prescaler 1 register (pre1) register f3h
z8 cpu user manual um001602-0904 counters and timers 129 it is suggested that p31 be con? gured as an input line by setting p3m re gister bit 5 to 0, although t in is still functional if p31 is con? gured as a handshak e input. each high-to-lo w transition on t in generates an interrupt request irq2, re g ardless of the selected t in mode or the enabled/disabled state of t1. irq2 must therefore be mask ed or enabled according to the requirements of the application. external clock input mode the t in external clock input mode (tmr bit 5 and bit 4 both set to 0) supports counting of e xternal e v ents, where an e v ent is considered to be a high-to-lo w transition on t in ( see figure 82 ) . see the product data sheet for the minimum allo wed t in e xternal clock input period (t p t in ). gated internal clock mode the t in gated internal clock mode (tmr bit 5 and bit 4 set to 0 and 1 respecti v ely) measures the duration of an e xternal e v ent. in this mode, the t1 prescaler is dri v en by the internal timer clock, g ated by a high le v el on figure 82. external cloc k input mode d p3 1 internal irq 2 tmr t in clock d pre1 t1 irq 5 d 5 Cd 4 = 00 clock
z8 family of microcontrollers user manual counters and timers um001602-0904 130 t in ( see figure 83 ) . t1 counts while t in is high and stops counting while t in is lo w . interrupt request irq2 is generated on the high-to-lo w tran - sition of t in signalling the end of the g ate input. interrupt request irq5 is generated if t1 reaches its end-of-count. triggered input mode the t in t riggered input mode (tmr bits 5 and 4 are set to 1 and 0, respecti v ely) causes t1 to start counting as the result of an e xternal e v ent ( see figure 84 ) . t1 is then loaded and clock ed by the internal timer clock follo wing the ? rst high-to-lo w transition on the t in input. subsequent t in transitions do not af fect t1. in single-p ass mode, the enable bit is reset whene v er t1 reaches its end-of-count. further t in transitions will ha v e no ef fect on t1 until softw are sets the enable count bit ag ain. in continuous mode, once t1 is triggered counting continues until softw are resets the enable count bit. interrupt request irq5 is generated when t1 reaches its end-of-count. figure 83. gated cloc k input mode osc 2 4 d d pre1 p3 1 t1 irq 2 t in irq 5 gate internal tmr d 5C d 4 = 01 clock
z8 cpu user manual um001602-0904 counters and timers 131 retriggerable input mode the t in retriggerable input mode (tmr bits 5 and 4 are set to 1) causes t1 to load and start counting on e v ery occurrence of a high-to-lo w tran - sition on t in ( see figure 84 ) . interrupt request irq5 will be generated if the programmed time interv al (determined by t1 prescaler and counter/ timer re gister initial v alues) has elapsed because the last high-to-lo w transition on t in . in single-p ass mode, the end-of-count resets the enable count bit. subsequent t in transitions will not cause t1 to load and start counting until softw are sets the enable count bit ag ain. in continuous mode, counting continues once t1 is triggered until softw are resets the enable count bit. when enabled, each high-to-lo w t in transition causes t1 to reload and restart counting. interrupt request irq5 is generated on e v ery end-of-count. figure 84. t rig g ered cloc k mode osc 2 4 d d pre1 tmr p3 1 t1 irq 2 t in irq 5 trigger d 5 Cd 4 = 11 internal tmr d 5 = 1 clock edge trigger
z8 family of microcontrollers user manual counters and timers um001602-0904 132 cascading counter/t imers f or some applications, it may be necessary to measure a time interv al greater than a single counter/timer can measure. in this case, t in and t out can be used to cascade t0 and t1 as a single unit ( see figure 85 ) . t0 should be con? gured to operate in continuous mode and to dri v e t out . t in should be con? gured as an e xternal clock input to t1 and wired back to t out . on e v ery other t0 end-of-count, t out under goes a high-to-lo w transition that causes t1 to count. t1 can operate in either single-p ass or continuous mode. when the t1 end-of-count is reached, interrupt request irq5 is generated. interrupt requests irq2 (t in high-to-lo w transitions) and irq4 (t0 end-of-count) are also generated b ut are most lik ely of no importance in this con? gura - tion and should be disabled. reset conditions after a hardw are reset, the counter/timers are disabled and the contents of the counter/timer and prescaler re gisters are unde? ned. ho we v er , the counting modes are con? gured for single-p ass and the t1 clock source is set for e xternal. figure 85. cascaded counter/timer s osc 2 4 pre0 t0 2 pre1 irq 2 p3 1 p3 6 t1 irq 4 t out t in irq 5
z8 cpu user manual um001602-0904 counters and timers 133 t in is set for external clock mode, and the t out mode is of f. figures 87 through 89 s ho w the binary reset v alues of the prescaler , counter/t imer , and t imer mode re gisters. figure 86. counter/timer reset figure 87. prescaler 1 register reset u u u u u u u u (%f4; write/read only) current value when read initial value when written (range 1 C2 56 decimal, 01 C0 0 hex) counter/timer 0 register r244 t0 (%f2; write/read only) counter/timer 1 register r242 t1 u u u u u u 0 0 ( % f 3 ; w r i t e - o n l y ) 1 = t 1 m o d u l o - n c o u n t m o d e 0 = t 1 s i n g l e p a s s p r e s c a l e r 1 r e g i s t e r r 2 4 3 p r e 1 0 1 C 0 0 h e x ) p r e s c a l e r m o d u l o ( r a n g e : 1 C 6 4 d e c i m a l c l o c k s o u r c e 0 = t 1 e x t e r n a l ( t i n ) 1 = t 1 i n t e r n a l
z8 family of microcontrollers user manual counters and timers um001602-0904 134 figure 88. prescaler 0 reset u u u u u u u 0 (%f5; write-only) 1 = t 0 modulo-n count mode 0 = t 0 single pass prescaler 0 register r245 pre0 01 C0 0 hex) prescaler modulo (range: 1 C6 4 decimal reserved (must be 0)
z8 cpu user manual um001602-0904 counters and timers 135 figure 89. timer mode register reset 0 0 0 0 0 0 0 0 (% f1; read/write) 0 = disable t 0 count 0 = no function 1 = load t 0 timer mode register r241 tmr 1 = enable t 0 count (retriggerable) t out modes: (non-retriggerable) trigger input = 10 t in = modes: external clock input = 00 gate input = 01 0 = no function 1 = load t 1 0 = disable t 1 count 1 = enable t 1 count t out off = 00 t 0 out = 01 t 1 out = 10 internal clock out = 11 trigger input = 11
z8 family of microcontrollers user manual counters and timers um001602-0904 136
z8 cpu user manual um001602-0904 interrupts 137 interrupts th e z8 ? cpu allo ws 6 dif ferent interrupts from a v ariety of sources; up to four e xternal inputs, the on-chip counter/t imer(s), softw are, and serial i/o peripherals. these interrupts can be mask ed and their priorities set by using the interrupt mask and the interrupt priority re gisters. all six inter - rupts can be globally disabled by resetting the master interrupt enable, bit 7 in the interrupt mask re gister , with a disable interrupt (di) instruction. interrupts are globally enabled by setting bit 7 with an enable interrupt (ei) instruction. there are three interrupt control re gisters: the interrupt request re gister (irq), the interrupt mask re gister (imr), and the interrupt priority re gis - ter (ipr). figure 90 s ho ws addresses and identi? ers for the interrupt con - trol re gisters. figure 91 i s a block diagram sho wing the interrupt mask and interrupt priority logic. figure 90. interrupt contr ol register s register hex 7 interrupt mask interrupt request interrupt priority identifier fbh fah f9h imr irq ipr
z8 family of microcontrollers user manual interrupts um001602-0904 138 th e z8 ? f amily supports both v ectored and polled interrupt handling. details on v ectored and polled interrupts can be found later in this chap - ter . see the selected z8 cpu's product speci? cation for the e xact interrupt sources supported. figure 91. interrupt bloc k dia gram irq irq 0 Cirq 5 vector select interrupt request imr ipr priority logic 6 global interrupt enable 6 note:
z8 cpu user manual um001602-0904 interrupts 139 interrupt sour ces t able 18 p resents the interrupt types, sources, and v ectors a v ailable in the z8 ? f amily of processors. external interrupt sources external sources in v olv e interrupt request lines irq0Cirq3. irq0, irq1, and irq2 can be generated by a transition on the corresponding port 3 pin (p32, p33, and p31 correspond to irq0, irq1, and irq2, respecti v ely). figure 92 i s a block diagram for interrupt sources irq0, irq1, and irq2. t able 18. interrupt t ypes, sources, and v ectors name sources v ector location c omments irq 0 da v 0 , irq 0 , comparator 0,1 external (p3 2 ), edge t riggered; internal irq 1 da v 1 , irq 1 2,3 external (p3 3 ), edge t riggered; internal irq 2 da v 2 , irq 2 , t in , comparator 4,5 external (p3 1 ), edge t riggered; internal irq 3 6,7 external (p3 0 ) or (p3 2 ), edge t riggered; internal serial in 6,7 internal t 0 8,9 internal serial out 8,9 internal irq 5 t 1 10,1 1 internal
z8 family of microcontrollers user manual interrupts um001602-0904 140 the interrupt sources and trigger conditions are de vice dependent. see the de vice product speci? cation to determine a v ailable sources (internal and e xternal), triggering edge options, and e xact programming details. when the port 3 pin (p31, p32, or p33) transitions, the ? rst ? ip-? op is set. the ne xt tw o ? ip-? ops synchronize the request to the internal clock and delay it by tw o internal clock periods. the output of the last ? ip-? op (irq0, irq1, or irq2) goes to the corresponding interrupt request re g - ister . irq3 can be generated from an e xternal source only if serial in is not enabled. otherwise, its source is internal. the e xternal request is gener - ated by a lo w edge signal on p30 as sho wn in figure 93 . ag ain, the e xter - nal request is synchronized and delayed before reaching irq3. some z8 products replace p30 with p32 as the e xternal source for irq3. in this case, irq3 interrupt generation follo ws the logic as illustrated in figure 92 . although interrupts are edge triggered, minimum interrupt request lo w and high times must be observ ed for proper operation. see the de vice product speci? cation for e xact timing requirements on e xternal interrupt requests (t w il, t w ih). figure 92. interrupt sour ces irq0-irq2 bloc k dia gram p3 n irq m system clock multiple input n = 2, 3, 1 and signal q s r conditioning circuitry m = 0,1,2 (internal) q d q d
z8 cpu user manual um001602-0904 interrupts 141 internal interrupt sources internal sources in v olv e interrupt requests irq0, irq2, irq3, irq4, and irq5. internal sources are ored with the e xternal sources, so either an internal or e xternal source can trigger the interrupt. internal interrupt sources and trigger conditions are de vice dependent. see the de vice product speci? cation to determine a v ailable sources, trig - gering edge options, and e xact programming details. f or more details on the internal interrupt sources, refer to the chapters describing the counter/ t imer , i/o ports, and serial i/o. interrupt request register logic and t iming figure 94 s ho ws the logic diagram for the interrupt request (irq) re gis - ter . the leading edge of the request will set the ? rst ? ip-? op, that will remain set until interrupt requests are sampled. requests are sampled internally during the last clock c ycle before an opcode fetch ( see figure 95 ) . external requests are sampled tw o internal figure 93. interrupt source irq3 block diagram q pin d serial receiver p3m 6 irq 3 clock irq 3 irq 3 external source (irq 3 serial in) internal source d q
z8 family of microcontrollers user manual interrupts um001602-0904 142 clocks earlier , due to the synchronizing ? ip-? ops sho wn in figures 92 and 93 . at sample time the request is transferred to the second ? ip-? op in figure 94 , t hat dri v es the interrupt mask and priority logic. when an inter - rupt c ycle occurs, this ? ip-? op will be reset only for the highest priority le v el that is enabled. the user has direct access to the second ? ip-? op by reading and writing the irq re gister . irq is read by specifying it as the source re gister of an instruction and written by specifying it as the destination re gister . figure 94. irq register logic q s from to mask irq 0 Ci rq5 r q r priority logic and priority logic sample clock
z8 cpu user manual um001602-0904 interrupts 143 interrupt initialization after reset, all interrupts are disabled and must be initialized before v ec - tored or polled interrupt processing can be gin. the interrupt priority re g - ister (ipr), interrupt mask re gister (imr), and interrupt request re gister (irq) must be initialized, in that order , to start the interrupt pro - cess. interrupt priority register initialization the interrupt priority re gister (ipr) sho wn in figure 96 i s a write-only re gister that sets priorities for the v ectored interrupts in order to resolv e simultaneous interrupt requests. (there are 48 sequence possibilities for interrupts.) the six interrupt le v els irq0-irq5 are di vided into three groups of tw o interrupt requests each. one group contains irq3 and irq5. the second group contains irq0 and irq2, while the third group contains irq1 and irq4. priorities can be set both within and between groups as sho wn in t ables 19 and 20 . bits 1, 2, and 5 de? ne the priority of the indi vidual members within the three groups. bits 0, 3, and 4 are encoded to de? ne six priority orders between the three groups. bits 6 and 7 are reserv ed. figure 95. interrupt request timing t1 t2 t3 t1 t2 t3 t1 t2 t3 external interrupt interrupt request sampled internally request sampled mn m1 m2
z8 family of microcontrollers user manual interrupts um001602-0904 144 figure 96. interrupt priority register t able 19. interrupt priority group bit v alue priority highest lowest c bit 1 0 irq1 irq4 1 irq4 irq1 b bit 2 0 irq2 irq0 1 irq0 irq2 d7 d6 d5 d4 d3 d2 d1 d0 (write-only) interrupt priority register (ipr) register f9h interrupt group priority bits priority 000 reserved 001 c > a > b 010 a > b > c 011 a > c > b 100 b > c > a 101 c > b > a 110 b > a > c 111 reserved 0 = irq1 > irq4 1 = irq4 > irq1 group c (irq1 and irq4 priority) reserved (must be 0) 0 = irq2 > irq0 1 = irq0 > irq2 group b (irq0 and irq2 priority) 0 = irq5 > irq3 1 = irq3 > irq5 group a (irq3 and irq5 priority)
z8 cpu user manual um001602-0904 interrupts 145 interrupt mask register initialization the interrupt mask re gister indi vidually or globally enables or d isables the six interrupt requests ( see figure 97 ) . when bit 0 to bit 5 are set to 1, the corresponding interrupt requests are enabled. bit 7 is the master enable and must be set before an y of the indi vidual interrupt requests can be recognized. resetting bit 7 globally disables all of the i nterrupt requests. bit 7 is set and reset by the ei and di instructions. it is automat - a bit 5 0 irq5 irq3 1 irq3 irq5 t able 20. interrupt group priority bit pattern group priority bit 4 bit 3 bit 0 high medium low 0 0 0 not used 0 0 1 c a b 0 1 0 a b c 0 1 1 a c b 1 0 0 b c a 1 0 1 c b a 1 1 0 b a c 1 1 1 not used t able 19. interrupt priority (continued) group bit v alue priority highest lowest
z8 family of microcontrollers user manual interrupts um001602-0904 146 ically reset during an interrupt service routine and set follo wing the e x e - cution of an interrupt return (iret) instruction. bit 7 must be reset by the di instruction before the contents of the inter - rupt mask re gister or the interrupt priority re gister are changed e xcept: ? immediately after a hardw are reset ? immediately after e x ecuting an interrupt service routine and before imr bit 7 has been set by an y instruction figure 97. interrupt mask register d7 d6 d5 d4 d3 d2 d1 d0 (read/write) interrupt request register (imr) register fbh 0 = disables irq0 1 = enables irq0 0 = disables irq1 1 = enables irq1 0 = disables irq2 1 = enables irq2 0 = disables irq3 1 = enables irq3 0 = disables irq4 1 = enables irq4 0 = disables irq5 1 = enables irq5 0 = disables ram protect 1 = enables ram protect 0 = disables interrupt 1 = enables interrupt
z8 cpu user manual um001602-0904 interrupts 147 the ram protect option is selected at r om mask submission time or at epr om program time. if not selected or not an a v ailable option, this bit is reserv ed and must be 0. interrupt request register initialization the i nterrupt request re gister (irq), sho wn in figure 98 , is a read/write re gister that stores the interrupt requests for both v ectored and polled interrupts. when an interrupt is made on an y of the six, the corresponding bit position in the re gister is set to 1. bit 0 to bit 5 are assigned to interrupt requests irq0 to irq5, respecti v ely . whene v er po wer -on reset (por) is e x ecuted, the irq resister is reset to 00h a nd disabled. before the irq re gister will accept requests, it must be enabled by e x ecuting an en able interr upts (ei) instruction. setting the global interrupt enable bit in the interrupt mask re gister (imr, bit 7) will not enable the irq. ex ecution of the ei instruction is required ( see figure 99 ) . f or polled processing, irq must still be initialized by an ei instruction. t o properly initialize the irq re gister , the follo wing code is pro vided. irq is al w ays cleared to 00h and is read only until the ? rst ei instruction, which enables the irq to be read/write. clr imr // ma ke sure v ectored interrupts are disabled. ei // en able irq register , otherwise read only . // no t required i f interrupts were previously enabled. di // di sable interrupt heading. note:
z8 family of microcontrollers user manual interrupts um001602-0904 148 imr is cleared before the irq enabling sequence to insure no une xpected interrupts occur when ei is e x ecuted. this code sequence should be e x e - cuted prior to programming the application required v alues for ipr and imr. irq bits 6 and 7 are de vice dependent. when reserv ed, the bits are not used and will return a 0 when read. when used as the interrupt edge select bits, the con? guration options are as sho w in t able 21 . figure 98. interrupt request register d7 d6 d5 d4 d3 d2 d1 d0 (read/write) reserved /int edge select interrupt request register (irq) register fah 0 = irq0 reset 1 = irq0 set 0 = irq1 reset 1 = irq1 set 0 = irq2 reset 1 = irq2 set 0 = irq3 reset 1 = irq3 set 0 = irq4 reset 1 = irq4 set 0 = irq5 reset 1 = irq5 set
z8 cpu user manual um001602-0904 interrupts 149 the proper sequence for programming the interrupt edge select bits is (assumes ipr and imr ha v e been pre viously initialized). t able 21. irq register configuration * irq interrupt edge d7 d6 p31 p32 0 0 f f 0 1 f r 1 0 r f 1 1 r/f r/f *note: f = falling edge; r = rising edge. di ;inhibit all interrupts until input edges are configured. or irq,#xx 000000 b ;configure interrupt ; do not disturb edges as requiredirq 0-5. ei ;re e nable interrupts. figure 99. irq reset functional logic dia gram s interrupt request register (irq, fah) reset el instruction por r
z8 family of microcontrollers user manual interrupts um001602-0904 150 irq softwar e interrupt generation irq can be used to generate softw are interrupts by specifying irq as the destination of an y instruction referencing the z8 ? s tandard re gister file. these softw are interrupts (swi) are controlled in the same manner as hardw are generated requests (in other w ords, the ipr and the imr control the priority and enabling of each swi le v el). t o generate a swi, the appropriate request bit in the irq is set as follo ws: orirq , # number where the immediate data, number, has a 1 in the bit position corre - sponding to the appropriate le v el of the swi. f or e xample, if an swi is required on irq5, number w ould ha v e a 1 in bit 5: or i rq, #00100000 b w ith this instruction, if the interrupt system is globally enabled, irq5 is enabled, and there are no higher priority pending requests, control is transferred to the service routine pointed to by the irq5 v ector . v ectored processing each z8 interrupt le v el has its o wn v ector . when an interrupt occurs, con - trol passes to the service routine pointed to by the interrupt s v ector loca - tion in program memory . the sequence of e v ents for v ectored interrupts is as follo ws: ? push pc lo w byte on stack ? push pc high byte on stack ? push fla gs on stack ? fetch high byte of v ector ? fetch lo w byte of v ector
z8 cpu user manual um001602-0904 interrupts 151 ? branch to service routine speci? ed by v ector figures 100 and 101 s ho w the v ectored interrupt operation. figure 100. eff ects of an interrupt on the stac k sp top of stack pc low byte pc high byte flags sp and stack after an interrupt sp sp and stack before an interrupt
z8 family of microcontrollers user manual interrupts um001602-0904 152 figure 101. interrupt vectoring pc high byte flags vector selected 000ch program memory interrupt service routine by priority logic interrupt vector table 0000h xxffh
z8 cpu user manual um001602-0904 interrupts 153 vectored interrupt cycle timing the interrupt ackno wledge c ycle time is 24 internal clock c ycles and is sho wn in figure 102 . in addition, tw o internal clock c ycles are required for the synchronizing ? ip-? ops. the maximum interrupt recognition time is equal to the number of clock c ycles required for the longest e x ecuting instruction present in the user program (assumes w orst case condition of interrupt sampling, figure 95 , just prior to the interrupt occurrence). t o calculate the w orst case interrupt latenc y (maximum time required from interrupt generation to fetch of the ? rst instruction of the interrupt service routine), sum these components: w orst case interrupt latenc y 24 int clk (interrupt ackno wledge time) + # t p c of longest instruction present in the user's application pro - gram + 2t p c (internal synchronization time). figure 102. z8 interrupt ac kno wledg e timing pc for stack external only pc+1 pc pcl sp-1 sp-2 pch sp-3 flags vect vect+1 even vector address odd vector address op code (discarded) vecth vectl first instruction of interrupt service routine for stack external only a0-a7 in internal clock as /ds a0-a7 out m3 m1 m2 m1 m2 stack push fetch vector high fetch vector low stack push stack push r/w
z8 family of microcontrollers user manual interrupts um001602-0904 154 nesting of vectored interrupts nesting of v ectored interrupts allo ws higher priority requests to interrupt a lo wer priority request. t o initiate v ectored interrupt nesting, do the fol - lo wing during the interrupt service routine: ? push the old imr on the stack ? load imr with a ne w mask to disable lo wer priority interrupts ? ex ecute ei instruction ? proceed with interrupt processing ? after processing is complete, e x ecute di instruction ? restore the imr to its original v alue by returning the pre vious mask from the stack ? ex ecute iret depending on the application, some simpli? cation of the abo v e procedure may be possible. p olled processing polled interrupt processing is supported by masking of f the irq to be polled. this is accomplished by clearing the corresponding bits in the imr. t o enable an y interrupt, ? rst the interrupt mechanism must be eng aged with an ei instruction. if only polled interrupts are to be serviced, e x e - cute: ei ;enable interrupt mechanism di ;disable v ectored interrupts. t o initiate polled processing, check the bits of interest in the irq using the t est under mask (tm) instruction. if the bit is set, call or branch to
z8 cpu user manual um001602-0904 interrupts 155 the service routine. the service routine services the request, resets its request bit in the irq, and branches or returns back to the main pro - gram. an e xample of a polling routine is as follo ws: in this e xample, if irq2 is being polled, maska will be 00000100b and maskb will be 11111011b . reset conditions upon reset, all bits in ipr are unde? ned. in imr, bit 7 is 0 and bits 0C6 are unde? ned. the irq re gister is reset and held in that state until an enable interrupt (ei) instruction is e x ecuted. tm i rq, #maska ;t est for request jr z , next ;if no request go to next call ser vice ;if request is there, then ;service it next : . . . ser vice: ;process request . . . and irq, #maskb ;clear request bit ret ;return to next
z8 family of microcontrollers user manual interrupts um001602-0904 156
z8 cpu user manual um001602-0904 power-down modes 157 p ow er-down modes i n addition to the standard run mode, the z8 ? cpu supports two power- down modes to minimize device current consumption. the two modes supported are hal t and st op . halt mode operation hal t mode suspends instruction e x ecution and turns of f the internal cpu clock. the on-chip oscillator circuit remains acti v e so the internal clock continues to run and is applied to the counter/t imer(s) and inter - rupt logic. t o enter h al t mode, it is necessary to ? rst ? ush the instruction pipeline to a v oid suspending e x ecution in mid-instruction. t o do this, the applica - tion program must e x ecute a nop instruction (opcode = ffh ) immedi - ately before the hal t instruction (opcode 7fh ), that is: ff n o p ; clear the instruction pipelin e 7f h al t ; enter hal t mod e hal t mode is e xited by interrupts, either e xternally or internally gener - ated. upon completion of the interrupt service routine, the user program continues from the instruction after hal t . hal t mode may also be e xited via a por/reset acti v ation or a w atchC dog t imer (wdt) time-out. (see the product data sheet for wdt a v ail - ability). in this case, program e x ecution will restart at the reset restart address 000ch . t o further reduce po wer consumption in hal t mode, some z8 f amily de vices allo w dynamic internal clock scaling. clock scaling may be accomplished on the ? y by reprogramming bit 0 and/or bit1 of the stop- mode reco v ery re gister (smr). see figure 103 on page 160 .
z8 family of microcontrollers user manual power-down modes um001602-0904 158 internal clock scaling directly af fects counter/t imer operationadjust - ment of the prescaler and do wncounter v alues may be required. t o deter - mine the actual hal t mode current (i cc1 ) v alue for the v arious optional modes a v ailable, see the related z8 de vice s product speci? cation. stop mode operation st op mode p ro vides the lo west possible de vice standby current. this instruction turns of f the on-chip oscillator and internal system clock. t o enter st op mode, it is necessary to ? rst ? ush the instruction pipeline to a v oid suspending e x ecution in mid-instruction. t o do this, the applica - tion program must e x ecute a nop instruction (opcode = ffh ) immedi - ately before the st op instruction (opcode = 6fh ), that is, f f n o p ; clear the instruction pipelin e 6f s t o p ; enter st op mod e st op mode i s e xited by an y one of the follo wing resets: po wer -on reset acti v ation, wdt time out (if a v ailable), or a stop-mode reco v ery source. upon reset generation, the processor will al w ays restart the application program at address 000ch . por/reset acti v ation is present on all z8 de vices and is implemented as a reset pin and/or an on-chip po wer on reset circuit. some z8 de vices allo w for the on-chip wdt to run in st op mode. if so acti v ated, the wdt time-out will generate a reset some ? x ed time period after entering st op mode. stop-mode reco v ery by the wdt will increase st op mode s tandby cur - rent (i cc2 ). this is due to the wdt clock and di vider circuitry that is no w enabled and running to support this reco v ery mode. see the product data sheet for actual i cc2 v alues. note:
z8 cpu user manual um001602-0904 power-down modes 159 all z8 de vices pro vide some form of dedicated stop-mode reco v ery (smr) circuitry . t w o smr methods are implementeda single ? x ed input pin or a ? e xible, programmable set of inputs. the selected z8 de vice product speci? cation should be re vie wed to determine the smr options a v ailable for use. f or de vices that support spi, the sla v e mode compare feature also serv es as a smr source. in the simple case, a lo w le v el applied to input pin p27 will trigger a smr. t o use this mode, pin p27 (i/o port 2, bit 7) must be con? gured as an input before st op mode i s entered. the lo w le v el on p27 must meet a minimum pulse width t wsm . (see the product data sheet) to trigger the de vice reset mode). some z8 de vices pro vide multiple smr input sources. the appropriate smr source is selected via the smr re gister . use of specialized smr modes (p2.7 input or smr re gister based) or the wdt time-out (only when in st op mode) pro vide a unique reset opera - tion. some control re gisters are initialized dif ferently for a smr/wdt triggered por than a standard reset operation. see the product speci? ca - tion (re gister ? le map) for e xact details. t o determine the actual st op mode current (i cc2 ) v alue for the optional smr modes a v ailable, see the selected z8 de vice s product data sheet. st op mode c urrent (i cc2 ) will be minimized when: ? v cc is at the lo w end of the de vices operating range ? wdt is of f in st op mode ? output current sourcing is minimized ? all inputs (digital and analog) are at the lo w or high rail v oltages
z8 family of microcontrollers user manual power-down modes um001602-0904 160 stop-mode reco v ery register this re gister selects the clock di vide v alue and determines the mode of stop-mode reco v ery ( see figure 103 ) . all bits are write-only , e xcept bit 7, that is read-only . bit 7 is a ? ag bit that is hardw are set on the condi - tion of stop-reco v ery and reset by a po wer -on c ycle. bit 6 controls whether a lo w le v el or a high le v el is required from the reco v ery source. bit 5 controls the reset delay after reco v ery . bits 2, 3, and 4, of the smr re gister , specify the source of the stop-mode reco v ery signal. bits 0 and 1 control internal clock di vider circuitry . the smr is located in bank f of the expanded re gister file at address 0bh . figure 103. stop-mode reco ver y register (w rite-only except bit d7, which is read-only) d7 d6 d5 d4 d3 d2 d1 d0 smr (fh) 0b stop-mode r ecovery source 000 por only and/or external reset 001 p30 010 p31 011 p32 100 p33 101 p27 110 p2 nor 0C3 111 p2 nor 0C7 0 off ** 1 on sclk tclk d ivide-by-16 0 off 1 on* stop delay 0 por* 1 stop recovery stop flag (read only) 0 sclk tclk = xtal 2* external clock divide by 2 0 low* 1 high stop recovery level 1 sclk tclk = xtal * default setting after reset. ** default setting after reset and stop-mode r ecovery.
z8 cpu user manual um001602-0904 power-down modes 161 the smr re gister is a v ailable in select z8 cpu products. refer to the de vice product speci? cation to determine smr options a v ailable. sclk tclk divide-by-16 select . this d0 bit of the smr controls a di vide-by-16 prescaler of sclk tclk. the purpose of this control is to selecti v ely reduce de vice po wer consumption during normal processor e x ecution (sclk control) and/or hal t mode (where tclk sources counter/timers and interrupt logic). external clock divide-by-t wo . this d1 bit can eliminate the oscillator di vide-by-tw o circuitry . when this bit is 0, the system clock (sclk) and t imer clock (tclk) are equal to the e xternal clock frequenc y di vided by tw o. the sclk tclk is equal to the e xternal clock frequenc y when this bit is set (d1 = 1). using this bit together with d7 of pcon helps fur - ther lo wer emi (d7 (pcon) = 0, d1 (smr) = 1). the def ault setting is zero. stop-mode recovery sour ce . the d2, d3, and d4 bits of the smr specify the w ak e-up source of the stop-reco v ery and ( t able 22 a nd figure 104 ) . t able 22. s top-mode r ecovery source smr: 432 description of operatio n d4 d3 d2 0 0 0 por and/or external reset recovery . 0 0 1 p30 transition . 0 1 0 p31 transition (not in analog mode) . 0 1 1 p32 transition (not in analog mode) . 1 0 0 p33 transition (not in analog mode) .
z8 family of microcontrollers user manual power-down modes um001602-0904 162 stop-mode recovery delay select . this d5 bit, if high, enables the t por reset delay after stop-mode reco v ery . the def ault con? guration of this bit is 1. if the fast w ak e up is selected, the stop-mode reco v ery source is k ept acti v e for at least 5 tpc. stop-mode recovery edge select . a 1 in this d6 bit position indicates that a high le v el on an y one of the reco v ery sources w ak es the z8 ? cpu from st op mode. a 0 indicates lo w-le v el reco v ery . the def ault is 0 on por ( see figure 104 ) . cold or w arm start . this d7 bit is set by the de vice upon entering st op mode. a 0 in this bit (cold) indicates that the de vice reset by por/ wdt reset . a 1 in this bit (w arm) indicates that the de vice a w ak ens by a smr source. 1 0 1 p27 transition . 1 1 0 logical nor of p20 through p23 . 1 1 1 logical nor of p20 through p27 . t able 22. s top-mode r ecovery source smr: 432 description of operatio n d4 d3 d2
z8 cpu user manual um001602-0904 power-down modes 163 if p31, p32, or p33 are to be used for a smr source, the digital mode of operation must be selected prior to entering st op mode. figure 104. stop-mode recovery source smr d4 d3 d2 0 0 0 smr d4 d3 d2 0 0 1 0 1 0 0 1 1 smr d4 d3 d2 1 0 0 smr d4 d3 d2 1 0 1 smr d4 d3 d2 1 1 0 smr d4 d3 d2 1 1 0 v dd p20 p23 p20 p27 p30 p33 p27 p31 p32 mux to por reset to p33 data latch and irq 1 stop mode recovery edge select (smr) p33 from pads digital/analog mode select (p3m)
z8 family of microcontrollers user manual power-down modes um001602-0904 164
z8 cpu user manual um001602-0904 serial input/output 165 serial input/output u art introduction select z8 cpu ? microcontrollers contain an on-board full-duple x uni - v ersal asynchronous recei v er/t ransmitter (u ar t) for data communica - tions. the u ar t consists of a serial i/o re gister (sio) located at address f0h , and its associated control logic ( see figure 105 ) . the sio is actually tw o re gisters, the recei v er b uf fer and the transmitter b uf fer , which are used in conjunction with counter/t imer t0 and port 3 i/o lines p30 (input) and p37 (output). counter/t imer t0 pro vides the clock input for control of the data rates. figure 105. u ar t bloc k dia gram stop bit detect transmitter shift register 6 parity gan serial out char detect receiver buffer receiver shift register serial in start bit detect clock control parity check shift clock shift clock 16 transfer stop start write foh reset read foh mark serial i/o clock (from t0) irq 4 internal data bus irq 3 p3 7 p3 0
z8 family of microcontrollers user manual serial input/output um001602-0904 166 con? guration of the u ar t is controlled by the port 3 mode re gister (p3m) located at address f7h . the z8 ? cpu al w ays transmits eight bits between the start and stop bits (eight data bits or se v en data bits and one p arity bit). odd parity generation and detection is supported. the sio re gister and its associated mode control re gisters are mapped into the standard z8 re gister file as sho wn in t able 23 . the or g anization allo ws the softw are to access the u ar t as general-purpose re gisters, eliminating the requirement for special instructions. u art bit-rate generation when port 3 mode re gister bit 6 is set to 1, the u ar t is enabled and t0 automatically becomes the bit rate generator ( see figure 106 ) . the end- of-count signal of t0 no longer generates interrupt request irq4. instead, the signal is used as the input to the di vide-by-16 counters (one each for the recei v er and the transmitter) that clock the data stream. t able 23. uart register map registe r n ame identifier he x a ddress port 3 mode p3m f7 t0 prescaler pre0 f5 t imer/counter0 t0 f4 t imer mode tmr f1 uar t sio f0
z8 cpu user manual um001602-0904 serial input/output 167 the di vide chain that generates the bit rate is sho wn in figure 107 . the bit rate is gi v en by the follo wing equation: bit rate = xt al frequency (2 x 4 x p x t x 16) where p and t are the initial v alues in prescaler0 and counter/t imer0, respecti v ely . the ? nal di vide-by-16 is required because t0 runs at 16 times the bit rate in order to synchronize on the incoming data. t o con? gure the z8 ? cpu for a speci? c bit rate, appropriate v alues as determined by the abo v e equation must be loaded into re gisters pre0 ( f5h ) and t0 ( f4h ). pre0 also controls the counting mode for t0 and should therefore be set to continuous mo de (d0 = 1). f or e xample, gi v en an input clock frequenc y (xt al) of 11.9808 mhz and a selected bit rate of 1200 bits per second, the equation is satis? ed by figure 106. p or t 3 mode register and bit-rate generation figure 107. bit rate divide chain d7 d6 d5 d4 d3 d2 d1 d0 (write-only) port 3 mode register (p3m) register f7h 0 p30 input and p37 = output 1 p30 serial in and p37 = serial out p t 16 bit rate 4 2 clock pre0 t0 f xtal
z8 family of microcontrollers user manual serial input/output um001602-0904 168 p = 39 and t = 2. counter/t imer t0 should be set to 02h . w ith t0 in con - tinuous mode, the v alue of pre0 becomes 9dh ( see figure 108 ) . t able 24 l ists se v eral commonly used bit rates and the v alues of xt al, p, and t required to deri v e them. this list is presented for con v enience and is not intended to be e xhausti v e. t able 24. bit rates bi t r ate 7,3728 7,9872 9,8304 1 1,0592 1 1,6736 1 1,9808 12,2880 p t p t p t p t p t p t p t 19200 3 1 C C 4 1 C C C C C C 5 1 9600 3 2 C C 4 2 9 1 C C C C 5 2 4800 3 4 13 1 4 4 9 2 19 1 C C 5 4 2400 3 8 13 2 4 8 9 4 19 2 39 1 5 8 1200 3 16 13 4 4 16 9 8 19 4 39 2 5 16 600 3 32 13 8 4 32 9 16 19 8 39 4 5 32 300 3 64 13 16 4 64 9 32 19 16 39 8 5 64 150 3 128 13 32 4 128 9 64 19 32 39 16 5 128 1 10 3 175 3 189 4 175 5 157 4 207 17 50 8 109
z8 cpu user manual um001602-0904 serial input/output 169 the bit rate generator is started by setting the t imer mode re gister (tmr) ( f1h ) bit 1 and bit 0 both to 1 ( see figure 109 ) . this transfers the contents of the prescaler 0 re gister and counter/t imer0 re gister to their corresponding do wn counters. in addition, counting is enabled so that u ar t operations be gin. figure 108. prescaler 0 register bit-rate generation figure 109. timer mode register bit rate generation d7 d6 d5 d4 d3 d2 d1 d0 (write-only) prescalar 0 register (pre0) register f5h count mode 0 = t 0 single pass (range: 1-64 decimal, 01hC00h) (range: 1-64) 1 = t 0 modulo-n d7 d6 d5 d4 d3 d2 d1 d0 (read/write) 0 = no function 1 = load t 0 timer mode register (tmr) register f1h 0 = disable t 0 count 1 = enable t 0 count
z8 family of microcontrollers user manual serial input/output um001602-0904 170 u art receiver operation the recei v er consists of a recei v er b uf fer (sio re gister [ f0h ]), a serial-in, parallel-out shift re gister , parity checking, and data synchronizing logic. the recei v er block diagram is sho wn as part of figure 105 on page 165 . receiver shift register after a hardw are reset or after a character has been recei v ed, the recei v er shift re gister is initialized to all 1s and the shift clock is stopped. serial data, input through port 3 bit 0, is synchronized to the internal clock by tw o d-type ? ip-? ops before being input to the shift re gister and the start bit detection circuitry . the start bit detection circuitry monitors the incoming data stream, look - ing for a start bit (a high-to-lo w input transition). when a start bit is detected, the shift clock logic is enabled. the t0 input is di vided-by-16 and, when the count equals eight, the di vider outputs a shift clock. this clock shifts the start bit into the recei v er shift re gister at the center of the bit time. before the shift actually occurs, the input is recheck ed to ensure that the start bit is v alid. if the detected start bit is f alse, the recei v er is reset and the process of looking for a start bit is repeated. if the start bit is v alid, the data is shifted into the shift re gister e v ery sixteen counts until a full character is assembled ( see figure 110 ) .
z8 cpu user manual um001602-0904 serial input/output 171 after a full character has been assembled in the recei v er s b uf fer , sio re gister ( f0h ), interrupt request irq3 is generated. the shift clock is stopped and the shift re gister reset to all 1s. the start bit detection cir - cuitry be gins monitoring the data input for the ne xt start bit. this c ycle allo ws the recei v er to synchronize on the center of the bit time for each incoming character . overwrites although the recei v er is single b uf fered, it is not protected from being o v erwritten, so the softw are must read the sio re gister ( f0h ) within one character time after the interrupt request (irq3). the z8 ? cpu does not ha v e a ? ag to indicate this o v errun condition. if polling is used, the irq3 bit in the interrupt request re gister must be reset by softw are. framing errors framing error detection is not supported by the recei v er hardw are, b ut by responding to the interrupt request within one character bit time, the soft - w are can test for a stop bit on p30. port 3 bits are al w ays readable, which figure 110. receiver timing shift register contents (r) shift rcvr start bit transition detected eight t0 counts later shifting starts stop bit one or more transferred to receive buffer and irq3 is generated rcvr data clock irq3
z8 family of microcontrollers user manual serial input/output um001602-0904 172 f acilitates break detection. f or e xample, if a null character is recei v ed, testing p30 results in a 0 being read. parity the data format supported by the recei v er must ha v e a start bit, eight data bits, and at least one stop bit. if parity is on, bit 7 of the data recei v ed will be replaced by a p arity error flag. a parity error sets bit 7 to 1, otherwise, bit d7 is set to 0. figure 111 s ho ws these data formats. the z8 ? cpu hardw are supports odd parity only , that is enabled by set - ting the port 3 mode re gister bit 7 to 1 ( see figure 112 ) . if e v en parity is required, p arity mo de should be disabled (p3m bit 7 set to 0), and soft - w are must calculate the recei v ed data s parity . figure 111. receiver data formats sp d7 d6 d5 d4 d3 d2 d1 d0 st eight data bits start bit start bit seven data bits one stop bit sp p d6 d5 d4 d3 d2 d1 d0 st parity error flag one stop bit received data (no parity) received data (with parity)
z8 cpu user manual um001602-0904 serial input/output 173 t ransmitter operation the transmitter consists of a transmitter b uf fer (sio re gister [ f0h ]), a parity generator , and associated control logic. the transmitter block dia - gram is sho wn as part of figure 105 on page 165 . after a hardw are reset or after a character has been transmitted, the trans - mitter is forced to a marking state (output al w ays high) until a character is loaded into the transmitter b uf fer , sio re gister ( f0h ). the transmitter is loaded by specifying the sio re gister as the destination re gister of an y instruction. t0 s output dri v es a di vide-by-16 counter that in turn generates a shift clock e v ery 16 counts. this counter is reset when the transmitter b uf fer is written by an instruction. this reset synchronizes the shift clock to the softw are. the transmitter then outputs one bit per shift clock, through port 3 bit 7, until a start bit, the character written to the b uf fer , and tw o stop bits ha v e been transmitted. after the second stop bit has been transmitted, the output is ag ain forced to a marking state. interrupt request irq4 is generated at this time to notify the processor that the transmitter is ready to accept another character . figure 112. p or t 3 mode register p arity d7 d6 d5 d4 d3 d2 d1 d0 (write-only) 0 = parity off 1 = parity on port 3 mode register (p3m) register f7h
z8 family of microcontrollers user manual serial input/output um001602-0904 174 overwrites the user is not protected from o v erwriting the transmitter , so it is up to the softw are to respond to irq4 appropriately . if polling is used, the irq4 bit in the interrupt request re gister must be reset. parity the data format supported by the transmitter has a start bit, eight data bits, and at least tw o stop bits. if parity is on, bit 7 of the data transmitted will be replaced by an odd parity bit. figure 113 s ho ws the transmitter data formats. p arity is enabled by setting port 3 mode re gister bit 7 to 1. if e v en parity is required, parity mode should be disabled (p3m bit 7 reset to 0), and softw are must modify the data to include e v en parity . because the transmitter can be o v erwritten, the user is able to generate a break signal. this is done by writing null characters to the transmitter b uf fer (sio re gister [ f0h ]) at a rate that does not allo w the stop bits to be output. each time the sio re gister is loaded, the di vide-by-16 counter is resynchronized and a ne w start bit is output follo wed by data.
z8 cpu user manual um001602-0904 serial input/output 175 u art reset conditions after a hardw are reset, the sio re gister contents are unde? ned, and serial mode and parity are disabled. figures 114 and 115 s ho w the binary reset v alues of the sio re gister and its associated mode re gister p3m. figure 113. t ransmitter data formats figure 114. sio register reset sp sp d7 d6 d5 d4 d3 d2 d1 d0 st eight data bits start bit start bit seven data bits two stop bit sp sp p d6 d5 d4 d3 d2 d1 d0 st odd parity two stop bit transmitted data (no parity) transmitted data (with parity) u u u u u u u u (read/write) serial data (d 0 = lsb) serial i/o register (sio) register rf0h
z8 family of microcontrollers user manual serial input/output um001602-0904 176 serial p eripheral interface select z8 microcontrollers incorporate a serial peripheral interf ace (spi) for communication with other microcontrollers and peripherals. the spi includes features such as stop-mode reco v ery , master/sla v e selection, and compare mode. t able 25 c ontains the pin con? guration for the spi feature when it is enabled. the spi consists of four re gisters: spi control re gister (scon), spi compare re gister (scomp), spi recei v e/buf fer re gister (rxb uf), and spi shift re gister . scon is located in bank (c) of the expanded re gister file at address 02. figure 115. p3m register reset 0 0 0 0 0 0 0 0 (write-only) 0 p32 = input p35 = output 1 p32 = dav0 /rdy0 p35 = rdy0/ dav0 0 port 2 pull-ups open-drain 1 port 2 pull-ups active 00 p33 = input p34 = output 01 p33 = input p34 = dm port 3 mode register (p3m) register f7h 10 p33 = input p34 = dm 11 p33 = dav1/ rdy1 p34 = rdy1/ dav1 0 p31 = input (t in ) p36 = output (t out ) 1 p32 = dav2 /rdy2 p36 = rdy2/ dav2 0 p30 = input p37 = output 1 p30 = serial in p37 = serial out 0 parity on 1 parity off
z8 cpu user manual um001602-0904 serial input/output 177 the spi control re gister (scon ; see figure 116 ) , is a read/write re gister that controls master/sla v e selection, interrupts, clock source and phase selection, and error ? ag. bit 0 enables/disables the spi with the def ault being spi disabled. a 1 in this location will enable the spi, and a 0 will disable the spi. bits 1 and 2 of the scon re gister in master mode select the clock rate. the user may choose whether internal clock is di vide-by-2, 4, 8, or 16. in sla v e mode, bit 1 of this re gister ? ags the user if an o v errun of the rxb uf re gister has occurred. the rxcharov errun ? ag is only reset by writing a 0 to this bit. in sla v e mode, bit 2 of the control re gister disables the data-out i/o function. if a 1 is written to this bit, the data-out pin is released to its original port con? guration. if a 0 is written to this bit, the spi shifts out one bit for each bit recei v ed. bit 3 of the scon re gister enables the compare feature of the spi, with the def ault being disabled. when the compare feature is enabled, a comparison of the v alue in the scomp re gister is made with the v alue in the rxb uf re gister . bit 4 sig - nals that a recei v e character is a v ailable in the rxb uf re gister . t able 25. spi pin configuration name function pin location di data-in p20 do data-out p27 ss slave select p35 sk spi clock p34
z8 family of microcontrollers user manual serial input/output um001602-0904 178 figure 116. spi contr ol register d7 d6 d5 d4 d3 d2 d1 d0 scon (c) 02 clk divide (m) 00 tclk/2 01 tclk/4 10 tclk/8 11 tclk/16 do spi port enable (s) 0 spi do port enable 1 do port to i/o 0 disable * 1 enable spi enable 0 enable 1 disable * compare enable 0 trans/fall 1 trans/rise clock phase 0 reset rxcharoverrun (s) 0 reset 1 char. avail rxcharavail 1 overrun (m) used with bit d7 equal to 1 * default setting after reset 0 tclk 1 timer 0 output clk source 0 slave 1 master master slave (s) used with bit d7 equal to 0
z8 cpu user manual um001602-0904 serial input/output 179 if the associated irq3 is enabled, an interrupt is generated. bit 5 controls the clock phase of the spi. a 1 in bit 5 allo ws for recei ving data on the clock s f alling edge and transmitting data on the clock s rising edge. a 0 allo ws recei ving data on the clock s rising edge and transmitting on the clock s f alling edge. the spi clock source is de? ned in bit 6. a 1 uses t imer0 output for the spi clock, and a 0 uses tclk for clocking the spi. finally , bit 7 determines whether the spi is used as a master or a sla v e. a 1 puts the spi into master mode and a 0 puts the spi into sla v e mode. spi operation the spi is used in one of tw o modes: either as system sla v e, or as system master . se v eral of the possible system con? gurations are sho wn in figure 117 . in s la v e mode, data transfer starts when the sla v e select (ss) pin goes acti v e. data is transferred into the sla v e s spi shift re gister through the di pin, which has the same address as the rxb uf re gister . after a byte of data has been recei v ed by the spi shift re gister , a recei v e character a v ailable (rca/irq3) ? ag and interrupt is generated. the ne xt byte of data will be recei v ed at this time. the rxb uf re gister must be cleared, or a recei v e character ov errun (rxcharov errun) ? ag will be set in the scon re gister , and the data in the rxb uf re gister will be o v er - written. when the communication between the master and sla v e is com - plete, the ss goes inacti v e.when the spi is acti v ated as a sla v e, it operates in all system modes: st op , hal t , and r un. unless disconnected, for e v ery bit that is transferred into the sla v e through the di pin, a bit is transferred out through the d0 pin on the oppo - site clock edge. during sla v e operation, the spi clock pin (sk) is an input. in master mode, the cpu must ? rst acti v ate a ss through one of its i/o ports. ne xt, data is transferred through the master s d0 pin one bit per master clock c ycle. loading data into the shift re gister initiates the trans - fer . in master mode, the master s clock will dri v e the sla v e s clock. at the conclusion of a transfer , a recei v e character a v ailable (rca/irq3) ? ag
z8 family of microcontrollers user manual serial input/output um001602-0904 180 and interrupt is generated. before data is transferred via the d0 pin, the spi enable bit in the scon re gister must be enabled. spi compar e when the spi compare enable bit, d3 of the scon re gister is set to 1, the spi compare feature is enabled. the compare feature is only v alid for sla v e mode. a compare transaction be gins when the (ss) line goes acti v e. data is recei v ed as if it were a normal transaction, b ut there is no data transmitted to a v oid b us contention with other sla v e de vices. when the compare byte is recei v ed, irq3 is not generated. instead, the data is com - pared with the contents of the scomp re gister . if the data does not match, do remains inacti v e and the sla v e ignores all data until the (ss) signal is reset. if the data recei v ed matches the data in the scomp re gis - ter , then a smr signal is generated. do is acti v ated if it is not tri-stated by d2 in the scon re gister , and data is recei v ed the same as an y other spi sla v e transaction. sla v es not comparing remain in their current mode, whereas sla v es comparing w ak e from a st op mode by means of an smr spi clock the spi clock maybe dri v en by three sources: t imer0, a di vision of the internal system clock, or the e xternal master when in sla v e mode. bit d6 of the scon re gister controls what source dri v es the spi clock. a 0 in bit d6 of the scon re gister determines the di vision of the internal system clock if this is used as the spi clock source. di vide by 2, 4, 8, or 16 is chosen as the scaler .
z8 cpu user manual um001602-0904 serial input/output 181 figure 117. spi system con? guration ss sk do di slave multiple slaves may have the same address ss1 ss4 do ss2 ss3 sk di master three wire compare setup ss sk do di slave ss sk do di slave ss sk do di slave ss sk do di master ss sk do di slave setup for compare ss sk do di slave ss sk do di slave ss sk do di slave ss sk do di master up to 256 slaves per ss line (1) (2) (255) (256) ss sk do di slave ss sk do di slave ss sk do di slave ss sk do di slave standard parallel setup ss sk do di slave standard serial setup ss sk do di slave ss sk do di slave ss sk do di slave ss sk do di master
z8 family of microcontrollers user manual serial input/output um001602-0904 182 recei ve character available and overrun when a complete data stream is recei v ed, an interrupt is generated and the rxchara v ail bit in the scon re gister is set. bit 4 in the scon re gister is for enabling or disabling the rxchara v ail interrupt. the rxchara v ail bit is a v ailable for interrupt polling purposes and is reset when the rxb uf re gister is read. rxchara v ail is generated in both master and sla v e modes. while in sla v e mode, if the rxb uf is not read before the ne xt data stream is recei v ed and loaded into the rxb uf re gister , recei v e character ov errun (rxcharov errun) occurs. because there is no require - ment for clock control in sla v e mode, bit d1 in the spi control re gister is used to log an y rxcharov errun (see figures 118 and 119 ) . figure 118. spi timing tsk ss sk d0 di 1 2 3 4 5
z8 cpu user manual um001602-0904 serial input/output 183 figure 119. spi logic spi compare register (scomp) ss d0 di sk port tclk smr bit control spi control spi receive buffer (rxbuf) spi shift register /interrupt control irq 3 sclk + n spi clock control
z8 family of microcontrollers user manual serial input/output um001602-0904 184 figure 120. spi data in/out con? guration p27 out pin spi active p27 in 0 soi d0 enable open-drain autolatch p27 p20 oe pin p20 in open-drain r 500 k ? autolatch p20 spi en spi do p27 oe spi spi do spi standard standard 1 p27 out *spi must be enabled with d0 d2 scon or spi di r 500 k ?
z8 cpu user manual um001602-0904 serial input/output 185 figure 121. spi cloc k/spi sla ve select output con? guration spi mstr pin p31 + spi en p34 sk in spi mstr pin p35 spi en ref ss 0 p34, p35 standard output 1 p34, p35 comparator output d0 p35 out pcon p32 ref + - p34 out - spi en sk out mux
z8 family of microcontrollers user manual serial input/output um001602-0904 186
z8 cpu user manual um001602-0904 external interface 187 external interface intr oduction th e z8 ? cpu can be a microcontroller with 20 pins for e xternal memory interf acing. the e xternal memory interf ace on the z8 ? cpu is generally for either ram or r om ; this features i s only a v ailable for de vices featur - ing port 0, port 1, r/ w , dm , as , and ds . please refer to speci? c product speci? cations for a v ailability of these features. th e z8 ? cpu of fers a multiple x ed e xternal memory interf ace. in m ulti - ple x ed mode, eight pins from port 1 form an address/data bus (ad7C ad0), eight pins from port 0 form a high address bus (a15Ca8). three additional pins pro vide the address strobe, data strobe, and the read/ write signal. figure 122 s ho ws the z8 ? cpu e xternal interf ace pins. figure 122. z8 ? cpu e xternal interface pins external z8 cpu program/data 64 kb each (port 1) ad7Cad0 (port 0) ad15Cad8 as ds r/ w dm
z8 family of microcontrollers user manual external interface um001602-0904 188 pin descriptions the follo wing sections brie? y describe the pins associated with the z8 ? cpu e xternal memory interf ace. a ddr ess str obe (output, active low ) . a ddress strobe (as) is pulsed lo w once at the be ginning of each machine c ycle. the rising edge of as indicates the address, read/write (r/ w ), and data memory ( dm ) signals are v alid for program or data memory transfers. in some cases, the z8 ? cpu address strobe is pulsed lo w re g ardless of accessing e xternal or internal memory . please refer to speci? c product speci? cations for as operation. d ata str obe (output, active low ) . d ata strobe (ds) pro vides the tim - ing for d ata mo v ement to or from the address/data b us for each e xternal memory transfer . during a write cycle, data out is v alid at the leading edge of the ds . during a read cycle, data in must be v alid prior to the trailing edge of the ds . r ead/w rite (output ) . r ead/write (r/w) determines the direction of data transfer f or memory transactions. r/ w is lo w when writing to pro - gram or data memory , and high for all other transactions. data memory (output) . data memory (dm) pro vides a signal to sepa - rate e xternal program memory from e xternal data memory . it is a pro - grammable function on pin p34. data memory is acti v e lo w for e xternal data memory accesses and high for e xternal program memory accesses. high addr ess lines a15Ca8 . a15Ca8 pro vide the high address lines for the memory interf ace. the port 0C1 mode re gisters must ha v e bits d7 and d1 set equal to 1 to con? gure port 0 as a15Ca8. outputs can be cmos- or ttl-compatible. please refer to product speci? cations for actual type. see figure 123 . addr ess/data lines ad7Cad0 . ad7Cad0 is a multiple x ed address/ data memory interf ace. the lo wer eight address lines (a7Ca0) are multi - ple x ed with data lines (d7Cd0). port 0C1 mode re gisters must ha v e bits
z8 cpu user manual um001602-0904 external interface 189 d4 set equal to 1 and d3 set equal to 0 to con? gure port 1 as ad7Cad0. inputs and outputs are ttl-compatible. see figure 123 . reset . r eset (input, acti v e lo w) initializes the z8 ? cpu . when reset is deacti v ated, program e x ecution be gins from program location 000ch . if held lo w , reset acts as a re gister ? le protect during po wer - do wn and po wer -up sequences. t o a v oid asynchronous and noisy reset problems, the z8 ? cpu is equipped with a reset ? lter of four e xternal clocks (4t p c). if the e xternal reset signal is less than 4t p c in duration, no reset will occur . on the ? fth clock after the reset is detected, an internal reset signal is latched and held for an internal re gister count of 18 or more e xternal clocks, or for the duration of the e xternal reset , which - e v er is longer . please refer to speci? c product speci? cations for length of reset delay time. crystal1, crystal2 (oscillator input and output) . these pins connect a parallel-resonant crystal, ceramic resonator , lc, rc netw ork, or e xter - nal single-phase clock to the on-chip oscillator input. please refer to the de vice product speci? cations for information on a v ailability of rc oscil - lator features. exter nal addressing con?guration the minimum b us con? guration uses port 1 as a multiple x ed address/data port (ad7Cad0), allo wing access to 256 bytes of e xternal memory . in this con? guration, the eight lo w-order bits (a0Ca7) are multiple x ed with the data (d7Cd0). port 0 can be programmed to pro vide either four additional address lines (a11Ca8), which increases the addressable memory to 4 kb, or eight additional address lines (a15Ca8), which increases the addressable e xter - nal memory up to 64 kb. it is required to add a nop after con? guring port 0/port 1 for e xternal addressing before jumping to e xternal memory e x ecution.
z8 family of microcontrollers user manual external interface um001602-0904 190 exter nal stacks the z8 ? cpu architecture supports stack operations in either the z8 ? standard re gister file or e xternal data memory . a stack s location is determined by bit 2 in the port 0C1 mode re gister ( f8h ). if bit 2 is set to 0, the stack is in e xternal data memory (see figure 124 ) . the instruction used to change the stack selection bit should not be imme - diately follo wed by the instructions ret or iret , because this will cause indeterminate program ? o w . after a reset , the internal stack is selected. figure 123. external address configuration d7 d6 d5 d4 d3 d2 d1 d0 (write-only) 01 = input 1x = a8Ca11 p00Cp07 mode 00 = output port 0C1 mode register (p01m) register f8h (p01m) 01 = byte output p04Cp07 mode 00 = output 01 = input 1x = a12Ca15 10 = ad0-ad7 00 = byte output p10Cp17 mode a8Ca15, as , ds , r/ w 11 = high impedance ad0 Ca d7,
z8 cpu user manual um001602-0904 external interface 191 please note that if port 0 is con? gured as a15Ca8 and the stack is selected as internal, an y stack operation will cause the contents in re gister feh to be displayed on port 0. data memory the tw o z8 e xternal memory spaces, data and program, are addressed as tw o separate spaces of up to 64 kb each. external program memory and e xternal data memory are logically selected by the data memory select output ( dm ). dm is made a v ailable on port 3, bit 4 (p34) by setting bit 4 and bit 3 in the port 3 mode re gister ( f7h ) to 10 or 01 ( see figure 125 ) . dm is acti v e lo w during the e x ecution of the lde, ldei instructions, and high for the e x ecution of program instructions. dm is also acti v e lo w during the e x ecution of call, pop , push, ret and iret instruc - tions if the stack resides in e xternal data memory . after a reset , dm is not selected. figure 124. z8 stac k selection d7 d6 d5 d4 d3 d2 d1 d0 (write-only) port 0C1 r egister register f8h (p01m) z8 stack selection 0 = external 1 = internal
z8 family of microcontrollers user manual external interface um001602-0904 192 bus operation t ypical data transfers between the z8 ? cpu a nd e x ternal me mory are illustrated in figures 126 and 127 . machine c ycles can v ary from six to 12 clock periods depending on the operation being performed. the notations used to describe the basic timing periods of the z8 ? cpu are machine c ycles (mn), timing states (tn), and clock periods. all timing references are made with respect to the output signals as and ds . the clock is sho wn for clarity only and does not ha v e a speci? c timing relationship with other signals. figure 125. p or t 3 data memor y operation d7 d6 d5 d4 d3 d2 d1 d0 (write-only) bits configuration 00 p33 = input p34 = output 01 p33 = input p34 = dm port 3 mode register register f7h (p3m) 10 p33 = input p34 = dm 11 p33 = d av1 /rdy1 p34 = rdy1/ d av1
z8 cpu user manual um001602-0904 external interface 193 figure 126. external instruction fetc h or memor y read cyc le machine cycle t1 t2* t3 clock a15-a8 ad7Cad0 as ds r/w dm read cycle a8-a15 a7Ca0 d7Cd0 i n *port inputs are strobed during t2, which is two internal systems clocks before the execution cycle of the current instruction.
z8 family of microcontrollers user manual external interface um001602-0904 194 address strobe all transactions start with as dri v en lo w and then raised high by the z8 ? cpu . the rising edge of as indicates that r/ w , dm (if used), and the address outputs are v alid. the address outputs (ad7Cad0), remain v alid only during mnt1 and typically must be latched using as . address figure 127. external memor y write cyc le machine cycle t1 t2 t3 clock a15-a8 ad7Cad0 as ds r/w dm write cycle a8-a15 a7Ca0 d7Cd0 o ut
z8 cpu user manual um001602-0904 external interface 195 outputs (a15Ca8) remain stable throughout the machine c ycle, re g ardless of the addressing mode. data strobe th e z8 ? cpu uses ds to time the actual data transfer . f or write opera - tions (r/ w = lo w), a lo w on ds indicates that v alid data is on the ad7C ad0 lines. f or read operations (r/w = high), the b us is placed in a high- impedance state before dri ving ds lo w , so the addressed de vice can put its data on the b us. th e z8 ? cpu samples this data prior to raising ds high. extended bus t iming some products can accommodate slo w memory access time by automati - cally inserting an additional softw are controlled state time (tx). this stretches the ds timing by tw o clock periods. figures 128 and 129 i llus - trate e xtended e xternal memory read and write c ycles.
z8 family of microcontrollers user manual external interface um001602-0904 196 figure 128. extended external instruction fetc h or memor y read cyc le machine cycle t2* tx t3 clock a15-a8 ad7Cad0 as ds r/w dm read cycle a15-a8 a7Ca0 d7Cd0 i n t1 *port inputs are strobed during t2, which is two internal system clocks before the execution of the current instruction.
z8 cpu user manual um001602-0904 external interface 197 t iming is e xtended by setting bit d5 in the port 0C1 mode re gister ( f8h ) to 1 ( see figure 130 ) . after a reset , this bit is set to 0. figure 129. extended external memor y write cyc le machine cycle t2 tx t3 clock a15-a8 ad7Cad0 as ds r/w dm write cycle a15Ca8 a7Ca0 d7Cd0 o ut t1
z8 family of microcontrollers user manual external interface um001602-0904 198 instruction t iming the high throughput of the z8 ? cpu is due, in part, to the use of an instruction pipeline, in which the instruction fetch and e x ecution c ycles are o v erlapped. during the e x ecution of the current instruction, the opcode of the ne xt instruction is fetched. instruction pipelining is illus - trated in figure 131 . figures 131 and 132 s ho w typical instruction c ycle timing for instructions fetched from memory . f or those instructions that require e x ecution time longer than that of the o v erlapped fetch, or reference program or data memory as part of their e x ecution, the pipe must be ? ushed. figures 131 and 132 a ssume the xt al 2 clock mode is selected. figure 130. extended bus timing d7 d6 d5 d4 d3 d2 d1 d0 (write-only) port 0C1 r egister register f8h (p01m) external memory timing 0 = normal 1 = extended
z8 cpu user manual um001602-0904 external interface 199 figure 131. instruction cyc le timing (1-byte instructions) t1 t2 t3 t3 t1 ds as r/w t1 t2 t2 fetch 1st byte t3 m1 m2 m3 a15Ca8 a15Ca8 a15Ca8 a7Ca0 a7Ca0 a7Ca0 a7Ca0 a7Ca0 fetch 1st byte of next instruction * port inputs are strobed during t2, which is two internal system clocks before the execution cycle of the current installation clock
z8 family of microcontrollers user manual external interface um001602-0904 200 z8 reset conditions after a hardw are reset, e xtended timing is set to accommodate slo w mem - ory access during the con? guration routine, dm is inacti v e, the stack resides in the re gister ? le. port 0, 1, and 2 are reset to input mode. port 2 is set to open-drain mode. figure 132. instruction cyc le timing (2- and 3-byte instructions) t1 t2 t3 t3 t1 ds as r/w t1 t2 t2 fetch 1st byte t3 m1 m2 m3 a15Ca8 a15Ca8 a15Ca8 a7Ca0 a7Ca0 a7Ca0 a7Ca0 a7Ca0 fetch 2nd byte fetch 3rd byte fetch 1st byte (1- or 2-byte instruction) (3-byte instruction) a15Ca8 a7Ca0 a7Ca0 clock *port inputs are strobed during t2, which is two internal system clocks before the execution cycle of the current instruction.
z8 cpu user manual um001602-0904 instruction set 201 instruction set z8 instructions can be di vided functionally into the follo wing eight groups: ? load ? bit manipulation ? arithmetic ? block t ransfer ? logical ? rotate and shift ? program control ? cpu control the follo wing summary sho ws the instructions belonging to each group and the number of operands required for each. the source operand is src, the destination operand is dst, and a condition code is cc. t able 26. load instructions mnemonic operands instruction clr dst clear ld dst, src load ldc dst, src load constant lde dst, src load external pop dst pop push src push
z8 family of microcontrollers user manual instruction set um001602-0904 202 t able 27. arithmetic instructions mnemonic operands instruction adc dst, src add with carry add dst, src add cp dst, src compare da dst decimal adjust dec dst decrement decw dst decrement w ord inc dst increment incw dst increment w ord sbc dst, src subtract with carry sub dst, src subtract t able 28. logical instructions mnemonic operands instruction and dst, src logical and com dst complement or dst, src logical or xor dst, src logical exclusive or t able 29. program control instructions mnemonic operands instruction call dst call procedure djnz dst, src decrement and jum p n on-zero
z8 cpu user manual um001602-0904 instruction set 203 iret interrupt return jp cc, dst jump jr cc, dst jump relative ret return t able 30. bit manipulation instructions mnemonic operands instruction tcm dst, src t est complemen t u nder mask tm dst, src t est under mask and dst, src bit clear or dst, src bit set xor dst, src bit complement t able 31. block t ransfer instructions mnemonic operands instruction ldci dst, src load constan t a uto increment ldei dst, src load externa l a uto increment t able 29. program control instructions (continued) mnemonic operands instruction
z8 family of microcontrollers user manual instruction set um001602-0904 204 t able 32. rotate and shift instructions mnemonic operands instruction rl dst rotate left rlc dst rotate left through carry rr dst rotate right rrc dst rotate right through carry sra dst shift right arithmetic sw ap dst swap nibbles t able 33. cpu control instructions mnemonic operands instruction ccf complement carry flag di disable interrupts ei enable interrupts hal t halt nop no operation rcf reset carry flag scf set carry flag srp src set register pointer st op stop wdh wdt enable during hal t wdt wdt enable or refresh
z8 cpu user manual um001602-0904 instruction set 205 pr ocessor flags the flag re gister (fch) informs the user of the current status of the z8 ? cpu . the ? ags and their bit positions in the flag re gister are sho wn in figure 133 . th e z8 ? flag re gister contains six bits of status information which are set or cleared by cpu operations. f our of the bits (c, v , z and s) can be tested for use with conditional jump instructions. t w o ? ags (h and d) cannot be tested and are used for bcd arithmetic. the tw o remaining bits in the flag re gister (f1 and f2) are a v ailable to the user , b ut the y must be set or cleared by instructions and are not usable with conditional jumps. as with bits in the other control re gisters, the flag re gister bits can be set or reset by instructions; ho we v er , only those instructions that do not af fect the ? ags as an outcome of the e x ecution should be used (load immedi - ate). the w atchCdog t imer (wdt) instruction af fects the flags accordingly: z = 1, s = 0, v = 0. figure 133. z8 fla g register note: d7 d6 d5 d4 d3 d2 d1 d0 flag register (read/write) half carry flag (h) user flag (f1) user flag (f2) register fch (flags) overflow flag (v) carry flag (c) decimal adjust flag (d) zero flag (z) sign flag (s)
z8 family of microcontrollers user manual instruction set um001602-0904 206 carry flag the carry flag (c) is set to 1 whene v er the result of an arithmetic opera - tion generates a carry or a borro w the high order bit 7. otherwise, the carry flag is cleared to 0. f ollo wing rotate and shift instructions, the carry flag contains the last v alue shifted out of the speci? ed re gister . an instruction can set, reset, or complement the carry flag. iret may change the v alue of the carry flag when the flag re gister , sa v ed in the stack, is restored. zero flag f or arithmetic and logical operations, the zero flag (z) is set to 1 if the result is zero. otherwise, the zero flag is cleared to 0. if the result of testing bits in a re gister is 00h , the zero flag is set to 1. otherwise the zero flag is cleared to 0. if the result of a rotate or shift operation is 00h , the zero flag is set to 1. otherwise, the zero flag is cleared to 0. iret changes the v alue of the zero flag when the flag re gister sa v ed in the stack is restored. the wdt instruction sets the zero flag to a 1. sign flag the sign flag (s) stores the v alue of the most signi? cant bit of a result follo wing an arithmetic, logical, rotate, or shift operation. when performing arithmetic operations on signed numbers, binary tw o s- complement notation is used to represent and process information. a pos - iti v e number is identi? ed by a 0 in the most signi? cant bit position (bit 7); therefore, the sign flag is also 0. a ne g ati v e number is identi? ed by a 1 in the most signi? cant bit position (bit 7); therefore, the sign flag is also 1.
z8 cpu user manual um001602-0904 instruction set 207 iret changes the v alue of the sign flag when the flag re gister sa v ed in the stack is restored. overflow flag f or signed arithmetic, rotate, and shift operations, the ov er? o w flag (v) is set to 1 when the result is greater than the maximum possible number (> 127) or less than the minimum possible number ( < C128) that can be represented in tw o s-complement form. the ov er? o w flag is set to 0 if no o v er? o w occurs. f ollo wing logical operations the ov er? o w flag is set to 0. iret changes the v alue of the ov er? o w flag when the flag re gister sa v ed in the stack is restored. decimal adjust flag the decimal adjust flag (d) is used for bcd arithmetic. because the algorithm for correcting bcd operations is dif ferent for addition and sub - traction, this ? ag speci? es what type of instruction w as last e x ecuted so that the subsequent decimal adjust (d a) operation can function properly . normally , the decimal adjust flag cannot be used as a test condition. after a subtraction, the decimal adjust flag is set to 1. f ollo wing an addition it is cleared to 0. iret changes the v alue of the decimal adjust flag when the flag re gis - ter sa v ed in the stack is restored. half carry flag the half carry flag (h) is set to 1 whene v er an addition generates a carry bit 3 (ov er? o w) or a subtraction generates a borro w bit 3. the half carry flag is used by the decimal adjust (d a) instruction to con v ert the binary result of a pre vious addition or subtraction into the correct decimal (bcd) result. as in the case of the decimal adjust flag, the user does not nor - mally access this ? ag.
z8 family of microcontrollers user manual instruction set um001602-0904 208 iret changes the v alue of the half carry flag when the flag re gister sa v ed in the stack is restored. condition codes the c, z, s, and v flags control the operation of the conditional jump instructions. sixteen frequently useful functions of the ? ag settings are encoded in a 4-bit ? eld called the condition code (cc), which forms bits 4- 7 of the conditional instructions. condition codes and ? ag settings are summarized in t ables 34 through 36 . notation for the ? ags and ho w the y are af fected are as follo ws: t able 34. z8 flag definitions flag description c carry flag z zero flag s sign flag v overflow flag d decimal adjust flag h half carry flag t able 35. flag settings definitions symbol definition 0 cleared to 0 1 set to 1 * set or cleared according to operation C unaf fected x undefined
z8 cpu user manual um001602-0904 instruction set 209 t able 36. condition codes binary hex mnemonic definition flag settings 0000 0 f always false 1000 8 (blank) always t rue 01 1 1 7 c carry c = 1 1 1 1 1 f nc no carry c = 0 01 10 6 z zero z = 1 1 1 10 e nz non-zero z = 0 1 101 d pl plus s = 0 0101 5 ml minus s = 1 0100 4 ov overflow v = 1 1 100 c nov no overflow v = 0 01 10 6 eq equal z = 1 1 1 10 e ne not equal z = 0 1001 9 ge greater than or equal (s xor v) = 0 0001 1 l t less than (s xor v) = 1 1010 a gt greater than (z or (s xor v)) = 0 0010 2 le less than or equal (z or (s xor v)) = 1 1 1 1 1 f uge unsigned greater than or equal c = 0 01 1 1 7 ul t unsigned less than c = 1 101 1 b ugt unsigned greater than (c = 0 and z = 0) = 1 001 1 3 ule unsigned less than or equal (c or z) = 1
z8 family of microcontrollers user manual instruction set um001602-0904 210 notation and binary encoding in the detailed instruction descriptions that mak e up the rest of this chap - ter , operands and status ? ags are represented by a notational shorthand. operands, condition codes, address modes, and their notations are as fol - lo ws ( t able 37 ). t able 37. notational shorthand notation address mode operand range * cc condition code see condition codes r w orking register rn n = 0 C1 5 r registe r reg reg. represents a number in the range of 00h to ffh or w orking register rn n = 0 C1 5 rr register pair reg reg. represents an even number in the range of 00h to feh or w orking register pair rrp p = 0, 2, 4, 6, 8, 10, 12, or 14 ir indirect w orking register @rn n = 0 C15 ir indirect register @reg reg. represents a number in the range of 00h to ffh or indirect w orking register @rn n = 0C 15 irr indirect w orking register pair @rrp p = 0, 2, 4, 6, 8, 10, 12, or 14 irr indirect register pair @reg reg. represents an even number in the range 00h to ffh *note: *see the device product specification to determine the exact register file range available. the register file size varie s by the device type.
z8 cpu user manual um001602-0904 instruction set 211 additional symbols used are listed in t able 38 . or w orking register pair @rrp p = 0, 2, 4, 6, 8, 10, 12, or 14 x indexed reg (rn) reg. represents a number in the range of 00h to ffh and n = 0 C1 5 da direct address addrs addrs. represents a number in the range of 00h to ffh ra relative address addrs addrs. represents a number in the range of +127 to C128 which is an of fset relative to the address of the next instruction im immediate #data data is a number between 00h to ffh t able 38. additional symbols symbol definition dst destination operand src source operand @ indirect address prefix sp stack pointer pc program counter flags flag register (fch) rp register pointer (fdh) t able 37. notational shorthand notation address mode operand range * *note: *see the device product specification to determine the exact register file range available. the register file size varie s by the device type.
z8 family of microcontrollers user manual instruction set um001602-0904 212 assignment of a v alue is indicated by the symbol . f or e xample, dst dst + src indicates the source data is added to the destination data and the result is stored in the destination location. the notation 'addr(n)' is used to refer to bit'n' of a gi v en location. f or e xample, dst (7) refers to bit 7 of the destination operand. assembly language syntax f or proper instruction e x ecution, z8 assembly language syntax requires dst, src be speci? ed, in that order . the follo wing instruction descriptions sho w the format of the object code produced by the assembler . this binary format should be follo wed by users who prefer manual program coding or who intend to implement their o wn assembler . example : if the contents of re gisters 43h and 08h are added and the result is stored in 43h , the assembly syntax and resulting object code is: imr interrupt mask register (fbh) # immediate operand prefix % hexadecimal number prefix h hexadecimal number suf fix b binary number suf fix opc opcode t able 38. additional symbols symbol definition
z8 cpu user manual um001602-0904 instruction set 213 in general, whene v er an instruction format requires an 8-bit re gister address, that address can specify an y re gister location in the range 0C255 or a w orking re gister r0Cr15. if, in the abo v e e xample, re gister 08h is a w orking re gister , the assembly syntax and resulting object code w ould be: see the de vice product speci? cation to determine the e xact re gister ? le range a v ailable. the re gister ? le size v aries by de vice type. z8 instruction summar y asm: add 43h, 08h (add dst, src) obj: 04 08 43 (opc src, dst) asm: add 43h, 08h (add dst, src) obj: 04 08 43 (opc src, dst) t able 39. summary of z8 instruction set instructio n a nd operation addres s m ode op cod e b yte (hex) flags affected dst src c z s v d h adc dst, src dst dst + src +c ? 1[ ] [ [ [ [ 0 [ add dst, sr c dst dst + src ? 0[ ] [ [ [ [ 0 [ and dst, sr c dst dst and src ? 5[ ] C [ [ 0 C C *note: these instructions have an identical set of addressing modes, which are encoded for brevity. the first opcode nibble is found in the instruction set table above. the second nibble is expressed symbolically by a [ ] in this table, and its value is found in the following table to the left of the applicable addressing mode pair. for example, the opcode of an adc instruction using the addressing modes r (destination) and ir (source) is 13.
z8 family of microcontrollers user manual instruction set um001602-0904 214 call dst da d6 C C C C C C sp sp C2 and pc dst or @ sp pc irr d4 ccf c not c ef [ C C C C C clr dst r b0 C C C C C C dst 0 ir b1 com dst r 60 C [ [ 0 C C dst not dst ir 61 cp dst, src dst ? src ? a[ ] [ [ [ [ C C da dst r 40 [ [ [ x C C dst da dst ir 41 dec dst r 00 C [ [ [ C C dst dst C1 ir 01 decw dst r r 80 C [ [ [ C C dst dst C1 ir 81 di dst imr(7) 0 8 f C C C C C C t able 39. summary of z8 instruction set instructio n a nd operation addres s m ode op cod e b yte (hex) flags affected dst src c z s v d h *note: these instructions have an identical set of addressing modes, which are encoded for brevity. the first opcode nibble is found in the instruction set table above. the second nibble is expressed symbolically by a [ ] in this table, and its value is found in the following table to the left of the applicable addressing mode pair. for example, the opcode of an adc instruction using the addressing modes r (destination) and ir (source) is 13.
z8 cpu user manual um001602-0904 instruction set 215 djnz r , dst ra ra C C C C C C r r C1 if r 0 pc pc + dst range:+127, C128 r = 0-f ei 9 f C C C C C C imr(7) 1 hal t 7 f C C C C C C inc dst dst dst + 1 r re C [ [ [ C C r = 0-f r 20 ir 21 incw dst rr a0 C [ [ [ C C dst dst + 1 ir a1 instruction and operation ad dress mode op code byte (he x) fla gs aff ected dst sr c c z s v d h t able 39. summary of z8 instruction set instructio n a nd operation addres s m ode op cod e b yte (hex) flags affected dst src c z s v d h *note: these instructions have an identical set of addressing modes, which are encoded for brevity. the first opcode nibble is found in the instruction set table above. the second nibble is expressed symbolically by a [ ] in this table, and its value is found in the following table to the left of the applicable addressing mode pair. for example, the opcode of an adc instruction using the addressing modes r (destination) and ir (source) is 13.
z8 family of microcontrollers user manual instruction set um001602-0904 216 iret flags @sp; sp sp + 1 pc @sp; sp sp + 2; and imr(7)C1 b f [ [ [ [ [ [ jp cc, dst da cd C C C C C C if cc is true, c = 0 Cf then pc dst irr 30 jr cc, dst ra cb C C C C C C if cc is true, pc pc + dst range: +127, C128 c = 0 Cf ld dst, src r im r c C C C C C C t able 39. summary of z8 instruction set instructio n a nd operation addres s m ode op cod e b yte (hex) flags affected dst src c z s v d h *note: these instructions have an identical set of addressing modes, which are encoded for brevity. the first opcode nibble is found in the instruction set table above. the second nibble is expressed symbolically by a [ ] in this table, and its value is found in the following table to the left of the applicable addressing mode pair. for example, the opcode of an adc instruction using the addressing modes r (destination) and ir (source) is 13.
z8 cpu user manual um001602-0904 instruction set 217 dst src r r r 8 r r r 9 r = 0 Cf r x c 7 x r d 7 r ir e 3 ir r f 3 r r e 4 r ir e 5 r im e 6 ir im e 7 ir r f 5 ldc dst, src r irr c 2 C C C C C C dst src lrr r d 2 ldci dst, src ir irr c 3 C C C C C C dst src r r + 1 or rr rr + 1 lrr ir d 3 lde dst, src r irr 82 C C C C C C t able 39. summary of z8 instruction set instructio n a nd operation addres s m ode op cod e b yte (hex) flags affected dst src c z s v d h *note: these instructions have an identical set of addressing modes, which are encoded for brevity. the first opcode nibble is found in the instruction set table above. the second nibble is expressed symbolically by a [ ] in this table, and its value is found in the following table to the left of the applicable addressing mode pair. for example, the opcode of an adc instruction using the addressing modes r (destination) and ir (source) is 13.
z8 family of microcontrollers user manual instruction set um001602-0904 218 dst src lrr r 92 ldei dst, src ir irr 83 C C C C C C dst src and r r + 1 or rr rr + 1 lrr ir 93 nop ff C C C C C C or dst, src dst dst or src ? 4[ ] C [ [ 0 C C pop dst r 50 C C C C C C dst @sp and sp sp + 1 ir 51 push src r 70 C C C C C C sp sp C1 and @sp src ir 71 rcf c 0 c f 0 C C C C C ret pc @sp; sp sp + 2 a f C C C C C C rl dst r ir 90 91 [ [ [ [ C C t able 39. summary of z8 instruction set instructio n a nd operation addres s m ode op cod e b yte (hex) flags affected dst src c z s v d h *note: these instructions have an identical set of addressing modes, which are encoded for brevity. the first opcode nibble is found in the instruction set table above. the second nibble is expressed symbolically by a [ ] in this table, and its value is found in the following table to the left of the applicable addressing mode pair. for example, the opcode of an adc instruction using the addressing modes r (destination) and ir (source) is 13. c 7 0
z8 cpu user manual um001602-0904 instruction set 219 rlc dst r ir 10 1 1 [ [ [ [ C C rr dst r ir e 0 e 1 [ [ [ [ C C rrc dst r c 0 [ [ [ [ C C ir c 1 sbc dst, src dst dstCsrcCc ? 3[ ] [ [ [ [ 1 [ scf c 1 d f 1 C C C C C sra dst r d 0 [ [ [ 0 C C ir d 1 srp dst rp src im 31 C C C C C C st op 6 f C C C C C C sub dst, src dst dstCsrc ? 2[ ] [ [ [ [ 1 [ t able 39. summary of z8 instruction set instructio n a nd operation addres s m ode op cod e b yte (hex) flags affected dst src c z s v d h *note: these instructions have an identical set of addressing modes, which are encoded for brevity. the first opcode nibble is found in the instruction set table above. the second nibble is expressed symbolically by a [ ] in this table, and its value is found in the following table to the left of the applicable addressing mode pair. for example, the opcode of an adc instruction using the addressing modes r (destination) and ir (source) is 13. c 7 0 c 7 0 c 7 0 c 7 0
z8 family of microcontrollers user manual instruction set um001602-0904 220 sw ap dst r ir f0 f1 x [ [ x C C tcm dst, src (not dst) and src ? 6[ ] C [ [ 0 C C tm dst, src dst and src ? 7[ ] C [ [ 0 C C wdh 4 f C x x x C C wdt 5 f C x x x C C xor dst, src dst and src xor src ? 7[ ] C [ [ 0 C C t able 39. summary of z8 instruction set instructio n a nd operation addres s m ode op cod e b yte (hex) flags affected dst src c z s v d h *note: these instructions have an identical set of addressing modes, which are encoded for brevity. the first opcode nibble is found in the instruction set table above. the second nibble is expressed symbolically by a [ ] in this table, and its value is found in the following table to the left of the applicable addressing mode pair. for example, the opcode of an adc instruction using the addressing modes r (destination) and ir (source) is 13. 7 4 3 0
z8 cpu user manual um001602-0904 instruction set 221 t able 40. summary of z8 ? address modes address mode lowe r o p code nibble dst src r r [2] r ir [3] r r [4] r ir [5] r im [6] ir im [7]
z8 family of microcontrollers user manual instruction set um001602-0904 222 op code map figure 134. op code map 10.5 cp r , r1 6.5 dec r1 6.5 dec ir1 6.5 add r1, r2 6.5 add r1, ir2 10.5 add r2, r1 10.5 add ir2, r1 10.5 add r1, im 10.5 add ir1, im 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f lower nibble (hex) bytes per instruction 2 3 2 3 1 6.5 rlc r1 6.5 rlc ir1 6.5 adc r1, r2 6.5 adc r1, ir2 10.5 adc r2, r1 10.5 adc ir2, r1 10.5 adc r1, im 10.5 adc ir1, im 6.5 inc r1 6.5 inc ir1 6.5 sub r1, r2 6.5 sub r1, ir2 10.5 sub r2, r1 10.5 sub ir2, r1 10.5 sub r1, im 10.5 sub ir1, im 10.5 decw rr1 10.5 decw ir1 6.5 rl r1 6.5 rl ir1 10.5 incw rr1 10.5 incw ir1 6.5 cp r1, r2 6.5 cp r1, ir2 10.5 cp r2, r1 10.5 cp ir2, r1 10.5 cp r1, im 10.5 cp ir1, im 6.5 clr r1 6.5 clr ir1 6.5 xor r1, r2 6.5 xor r1, ir2 10.5 xor r2, r1 10.5 xor ir2, r1 10.5 xor r1, im 10.5 xor ir1, im 6.5 rrc r1 6.5 rrc ir1 12.0 ldc r1, irr2 18.0 ldci ir1, irr2 10.5 ld r1,x,r2 6.5 sra r1 6.5 sra ir1 20.0 call* irr1 20.0 call da 10.5 ld r2,x,r1 6.5 rr r1 6.5 rr ir1 6.5 ld r1, ir2 10.5 ld r2, r1 10.5 ld ir2, r1 10.5 ld r1, im 10.5 ld ir1, im 8.5 sw ap r1 8.5 sw ap ir1 6.5 ld ir1, r2 10.5 ld r2, ir1 6.5 ld r1, r2 6.5 ld r2, r1 12/10.5 djnz r1, ra 12/10.0 jr cc, ra 6.5 ld r1, im 12.10.0 jp cc, da 6.5 inc r1 6.0 st op 7.0 hal t 6.1 di 6.1 ei 14.0 ret 16.0 iret 6.5 rcf 6.5 scf 6.5 ccf 6.0 nop 2 4 a lower op code nibble pipeline cycles mnemonic second operand fetch cycles upper op code nibble first operand legend: r = 8-bit addr ess r = 4-bit addr ess r1 or r1 = dst addr ess r2 or r2 = sr c addr ess sequence: opcode, first operand, second operand note: blank ar eas ar e r eserved. * 2-byte instruction appears as a 3-byte instruction 8.0 jp irr1 6.1 srp im 6.5 sbc r1, r2 6.5 sbc r1, ir2 10.5 sbc r2, r1 10.5 sbc ir2, r1 10.5 sbc r1, im 10.5 sbc ir1, im 8.5 da r1 8.5 da ir1 6.5 or r1, r2 6.5 or r1, ir2 10.5 or r2, r1 10.5 or ir2, r1 10.5 or r1, im 10.5 or ir1, im 10.5 pop r1 10.5 pop ir1 6.5 and r1, r2 6.5 and r1, ir2 10.5 and r2, r1 10.5 and ir2, r1 10.5 and r1, im 10.5 and ir1, im 6.5 com r1 6.5 com ir1 6.5 tcm r1, r2 6.5 tcm r1, ir2 10.5 tcm r2, r1 10.5 tcm ir2, r1 10.5 tcm r1, im 10.5 tcm ir1, im 10/12.1 push r2 12/14.1 push ir2 6.5 tm r1, r2 6.5 tm r1, ir2 10.5 tm r2, r1 10.5 tm ir2, r1 10.5 tm r1, im 10.5 tm ir1, im 6.0 wdt 6.0 wdh upper nibble (hex) 12.0 ldc lrr1, r2 18.0 ldci lrr1, ir2 12.0 lde r1, lrr2 18.0 ldei lr1, lrr2 12.0 lde r2, lrr1 18.0 ldei lr2, lrr1
z8 cpu user manual um001602-0904 instruction description 223 instruction description t able 41 contains a brief description of each of the ztp process manipu - lation functions. use the h yperlinks in t able 41 to jump quickly to more complete descriptions. t able 41. process manipulation functions add logical or add with carry logical exclusive or call procedure pop complement carry flag push clear reset carry flag complement return compare rotate left decimal adjust rotate left through carry decrement rotate right decrement and jump if non-zero rotate right through carry decrement w ord set carry flag disable interrupts set register pointer enable interrupts shift right arithmetic halt rotate right through carry increment set carry flag increment w ord set register pointer interrupt return shift right arithmetic jump stop jump relative subtract load subtract with carry
z8 family of microcontrollers user manual instruction description um001602-0904 224 load constant swap nibbles load constant autoincrement t est complement under mask load external data t est under mask load external data autoincrement w atch-dog t imer no operation w atch-dog t imer enable during halt mode logical and t able 41. process manipulation functions (continued)
z8 cpu user manual um001602-0904 instruction description 225 add add dst, src instruction format operation dst dst + src the source operand is added to the destination operand. t w o s comple - ment addition is performed. the sum is stored in the destination operand. the contents of the source operand are not af fected. cycles opc (hex) address mode d st s rc opc dst src 6 02 r r 6 03 r lr opc src dst 10 04 r r 10 05 r ir opc dst src 10 06 r im 10 07 ir im flags description c set if there is a carry from the most significant bit of the result; cleared otherwise. z set if the result is zero; cleared otherwise. s set if the result is negative; cleared otherwise. v set if an arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d always cleared. h set if there is a carry from the most significant bit of the low order four bits of the result; cleared otherwise.
z8 family of microcontrollers user manual instruction description um001602-0904 226 address modes r or ir can be used to specify a 4-bit w orking re gister . in this format, the source or destination w orking re gister operand is speci - ? ed by adding 1110b ( eh ) to the high nibble of the operand. f or e xample, if w orking re gister r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example if w orking re gister r3 contains 16h a nd w orking re gister r11 contains 20h , the statement: add r3, r11 op code: 02 3b lea v es the v alue 36h in w orking re gister r3. the c, z, s, v , d, and h flags are all cleared. example if w orking re gister r16 contains 16h , w orking re gister r10 contains 20h , and re gister 20h contains 11h , the statement: add r16, @r10 op code: 03 fa lea v es the v alue 27h in w orking re gister r16. the c, z, s, v , d, and h flags are all cleared. example if re gister 34h contains 2eh and re gister 12h contains 1bh , the state - ment: add 34h , 12h op code: 04 12 34 lea v es the v alue 49h in re gister 34h . the h flag is set, and the c, z, s, v , and d ? ags are cleared. e src or e dst note:
z8 cpu user manual um001602-0904 instruction description 227 example if re gister 4bh contains 82h , w orking re gister r3 contains 10h , and re gister 10h contains 01h , the statement: add 3eh, @r3 op code: 05 e3 4b lea v es the v alue 83h in re gister 4bh . the s flag is set, and the c, z, v , d, and h ? ags are cleared. example if re gister 6ch contains 2ah , the statement: add 6ch, #03h op code: 06 6c 03 lea v es the v alue 2dh in re gister 6ch . the c, z, s, v , d, and h flags are all cleared. example if re gister d4h contains 5fh and re gister 5fh contains 4ch , the state - ment: add @ d4h , #02h op code: 07 d4 02 lea v es the v alue 4eh in re gister 5fh . the c, z, s, v , d, and h flags are all cleared.
z8 family of microcontrollers user manual instruction description um001602-0904 228 add w ith carry syntax adc dst, src instruction format operation dst dst + src + c the source operand, along with the setting of the carry (c) flag, is added to the destination operand. t w o s complement addition is performed. the sum is stored in the destination operand. the contents of the source oper - and are not af fected. in multiple precision arithmetic, this instruction per - mits the carry from the addition of lo w order operands to be carried into the addition of high order operands. cycles opc (hex) address mode d st s rc opc dst src 6 02 r r 6 03 r lr opc src dst 10 04 r r 10 05 r ir opc dst src 10 06 r im 10 07 ir im
z8 cpu user manual um001602-0904 instruction description 229 address modes r or ir can be used to specify a 4-bit w orking re gister . in this format, the source or destination w orking re gister operand is speci - ? ed by adding 1110b ( eh ) to the high nibble of the operand. f or e xample, if w orking re gister r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example if w orking re gister r3 contains 16h , the c flag is set to 1, and w orking re gister r11 contains 20h , the statement: adc r3, r11 op code: 12 3b lea v es the v alue 37h in w orking re gister r3. the c, z, s, v , d, and h flags are all cleared. example if w orking re gister r16 contains 16h , the c flag is not set, w orking re gister r10 contains 20h , and re gister 20h contains 11h , the statement: adc r16, @r10 op code: 13 fa flag description c set if there is a carry from the most significant bit of the result; cleared otherwise. z set if the result is zero; cleared otherwise. s set if the result is negative; cleared otherwise. v set if an arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d always cleared. h set if there is a carry from the most significant bit of the low order four bits of the result; cleared otherwise. e src or e dst note:
z8 family of microcontrollers user manual instruction description um001602-0904 230 lea v es the v alue 27h in w orking re gister r16. the c, z, s, v , d, and h flags are all cleared. example if re gister 34h contains 2eh , the c flag is set, and re gister 12h contains 1bh , the statement: adc 34h , 12h op code: 14 12 34 lea v es the v alue 4ah in re gister 34h . the h flag is set, and the c, z, s, v , and d ? ags are cleared. example if re gister 4bh contains 82h , the c flag is set, w orking re gister r3 con - tains 10h , and re gister 10h contains 01h , the statement: adc 4bh , @r3 op code: 15 e3 4b lea v es the v alue 84h in re gister 4bh . the s flag is set, and the c, z, v , d, and h ? ags are cleared. example if re gister 6ch contains 2ah , and the c flag is not set, the statement: adc 6ch, #03h op code: 16 6c 03 lea v es the v alue 2dh in re gister 6ch . the c, z, s, v , d, and h flags are all cleared. example if re gister d4h contains 5fh , re gister 5fh contains 4ch , and the c flag is set, the statement: adc @ d4h , #02h op code: 17 d4 02
z8 cpu user manual um001602-0904 instruction description 231 lea v es the v alue 4fh in re gister 5fh . the c, z, s, v , d, and h flags are all cleared.
z8 family of microcontrollers user manual instruction description um001602-0904 232 call procedure call dst instruction format operation sp sp? @sp pc pc dst the stack pointer is decremented by tw o, the current contents of the pro - gram counter (pc) (address of the ? rst instruction follo wing the call instruction) are pushed onto the top of the stack, and the speci? ed desti - nation address is then loaded into the pc. the pc no w points to the ? rst instruction of the procedure. at the end of the procedure a ret (return) instruction can be used to return to the original program ? o w . ret will pop the top of the stack and replace the original v alue into the pc. cycles opc (hex) address mode dst opc dst 20 d6 da opc dst 20 d4 irr flag description c unaf fected z unaf fected s unaf fected v unaf fected d unaf fected h unaf fected
z8 cpu user manual um001602-0904 instruction description 233 address mode irr can be used to specify a 4-bit w orking re gister p air . in this format, the destination w orking re gister p air operand is speci? ed by adding 1110b ( eh ) to the high nibble of the operand. f or e xample, if w orking re gister p air rr12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example if the contents of the pc are 1a47h and the contents of the sp (re gisters feh and ffh ) are 3002h, the statement: call 3521h op code: d6 35 21 causes the sp to be decremented to 3000h , 1a4ah (the address follo wing the call instruction) to be stored in e xternal data memory 3000 and 3001h, and the pc to be loaded with 3521h . the pc no w points to the address of the ? rst statement in the procedure to be e x ecuted. example if the contents of the pc are 1a47h, the contents of the sp (re gister ffh ) are 72h, the contents of re gister a4h are 34h , and the contents of re gis - ter p air 34h are 3521h , the statement: call @a4h op code: d4 a4 causes the sp to be decremented to 70h , 1a4ah (the address follo wing the call instruction) to be stored in r70h and 71h , and the pc to be loaded with 3521h . the pc no w points to the address of the ? rst state - ment in the procedure to be e x ecuted. e src or e dst note:
z8 family of microcontrollers user manual instruction description um001602-0904 234 complement carry flag ccf instruction format operation c not c the c flag is complemented. if c = 1, then it is changed to c = 0; or , if c = 0, then it is changed to c = 1. example if the c flag contains a 0, the statement: ccf op code: ef will change the c flag from c = 0 to c = 1. cycles opc (hex) opc 6 ef flag description c complemented z unaf fected s unaf fected v unaf fected d unaf fected h unaf fected
z8 cpu user manual um001602-0904 instruction description 235 clear clr dst instruction format operation dst 0 the destination operand is cleared to 00h . address modes r or ir can be used to specify a 4-bit w orking re gister . in this format, the destination w orking re gister operand is speci? ed by add - ing 1110b ( eh ) to the high nibble of the operand. f or e xample, if w orking re gister r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example if w orking re gister r6 contains afh, the statement: clr r6 op code: b0 e6 cycles opc (hex) address dst opc dst 6 80 r 6 81 ir flag description c unaf fected z unaf fected s unaf fected v unaf fected d unaf fected h unaf fected e dst note:
z8 family of microcontrollers user manual instruction description um001602-0904 236 will lea v e the v alue 00h in w orking re gister r6. if re gister a5h contains the v alue 23h , and re gister 23h contains the v alue fch , the statement: clr @a5h op code: b1 a5 will lea v e the v alue 00h in re gister 23h .
z8 cpu user manual um001602-0904 instruction description 237 complement com dst instruction format operation dst not dst the contents of the destination operand are complemented (one s comple - ment). all 1 bits are changed to 0, and all 0 bits are changed to 1. address modes r or ir can be used to specify a 4-bit w orking re gister . in this format, the destination w orking re gister operand is speci? ed by add - ing 1110b ( eh ) to the high nibble of the operand. f or e xample, if w orking re gister r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example if re gister 08h contains 24h ( 00100100b ), the statement: cycles opc (hex) address mode dst opc dst 6 60 r 6 61 ir flag description c unaf fected z set if the result is zero; cleared otherwise. s set if result bit 7 is set; cleared otherwise. v always reset to 0. d unaf fected h unaf fected e dst note:
z8 family of microcontrollers user manual instruction description um001602-0904 238 com 08h op code: 60 08 lea v es the v alue dbh ( 11011011 ) in re gister 08h . the s flag is set, and the z and v ? ags are cleared. example if re gister 08h contains 24h , and re gister 24h contains ffh ( 11111111b ), the statement: com @08h op code: 61 08 lea v es the v alue 00h ( 00000000b ) in re gister 24h . the z flag is set, and the v and s ? ags are cleared.
z8 cpu user manual um001602-0904 instruction description 239 compare cp dst, src instruction format operation dst?rc the source operand is compared to (subtracted from) the destination operand, and the appropriate ? ags are set accordingly . the contents of both operands are unaf fected. address modes r or ir can be used to specify a 4-bit w orking re gister . in this format, the source or destination w orking re gister operand is speci - ? ed by adding 1110b ( eh ) to the high nibble of the operand. f or e xample, cycles opc (hex) address mode d st s rc opc dst src 6 a2 r r 6 a3 r lr opc src dst 10 a4 r r 10 a5 r ir opc dst src 10 a6 r im 10 a7 ir im flag description c cleared if there is a carry from the most significant bit of the result. set otherwise indicating a borrow . z set if the result is zero; cleared otherwise. s set if result bit 7 is set (negative); cleared otherwise. v set if arithmetic overflow occurs; cleared otherwise. d unaf fected h unaf fected note:
z8 family of microcontrollers user manual instruction description um001602-0904 240 if w orking re gister r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example if w orking re gister r3 contains 16h a nd w orking re gister r11 contains 20h , the statement: cp r3, r11 op code: a2 3b sets the c and s flags, and the z and v ? ags are cleared. example if w orking re gister r15 contains 16h , w orking re gister r10 contains 20h , and re gister 20h contains 11h , the statement: cp r16, @r10 op code: a3 fa clears the c, z, s, and v flags. example if re gister 34h contains 2eh and re gister 12h contains 1bh , the state - ment: cp 34h , 12h op code: a4 12 34 clears the c, z, s, and v flags. example if re gister 4bh contains 82h , w orking re gister r3 contains 10h , and re gister 10h contains 01h , the statement: cp 4bh , @r3 op code: a5 e3 4b e src or e dst
z8 cpu user manual um001602-0904 instruction description 241 sets the s flag, and clears the c, z, and v flags. example if re gister 6ch contains 2ah , the statement: cp 6ch, # 2ah op code: a6 6c 2a sets the z flag, and the c, s, and v flags are all cleared. example if re gister d4h contains fch , and re gister fch contains 8fh , the state - ment: cp @ d4h , 7fh op code: a7 d4 ff sets the v flag, and the c, z, and s flags are all cleared.
z8 family of microcontrollers user manual instruction description um001602-0904 242 decimal adjust da dst instruction format operation dst da dst the destination operand is adjusted to form tw o 4-bit bcd digits follo w - ing a binary addition or subtraction operation on bcd encoded bytes. f or addition (add and adc) or subtraction (sub and sbc), the follo wing table indicates the operation performed. cycles opc (hex) address mode dst opc dst 8 40 r 8 41 ir instruction carr y b efor e d a bits 7 C4 v alu e ( hex) h fla g b efor e d a bits 3 C0 v alu e ( hex) numbe r a dded t o b yte carr y a fte r d a 0 0 C9 0 0 C9 00 0 0 0 C8 0 a Cf 06 0 0 0 C9 1 0 C3 06 0 add 0 a Cf 0 0 C9 60 1 adc 0 9 Cf 0 a Cf 66 1 0 a Cf 1 0 C3 66 1 1 0 C2 0 0 C9 60 1 1 0 C2 0 a Cf 66 1 1 0 C3 1 0 C3 66 1 0 0 C9 0 0 C9 00 0 sub 0 0 C8 1 6 Cf f a 0
z8 cpu user manual um001602-0904 instruction description 243 if the destination operand is not the result of a v alid addition or subtrac - tion of bcd digits, the operation is unde? ned. address modes r or ir can be used to specify a 4-bit w orking re gister . in this format, the destination w orking re gister operand is speci? ed by add - ing 1110b ( eh ) to the high nibble of the operand. f or e xample, if w orking re gister r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example if addition is performed using the bcd v alue 15 and 27, the result should be 42. the sum is incorrect, ho we v er , when the binary representations are added in the destination location using standard binary arithmetic. 0 001 0101 = 15h + 0 010 0111 = 27 h 0 011 1100 = 3c h sbc 1 7 Cf 0 0 C9 a0 1 1 6 Cf 1 6 Cf 9a 1 flag description c set if there is a carry from the most significant bit; cleared otherwise (see table above). z set if the result is zero; cleared otherwise. s set if result bit 7 is set (negative); cleared otherwise. d unaf fected h unaf fected e dst instruction carr y b efor e d a bits 7 C4 v alu e ( hex) h fla g b efor e d a bits 3 C0 v alu e ( hex) numbe r a dded t o b yte carr y a fte r d a note:
z8 family of microcontrollers user manual instruction description um001602-0904 244 if the result of the addition is stored in re gister 5fh , the statement: da 5fh op code: 40 5f adjusts this result so the correct bcd representation is obtained. 0 011 1100 = 3ch 0000 0110 = 06h 0100 0010 = 42 h re gister 5fh no w contains the v alue 42h . the c, z, and s ? ags are cleared, and v is unde? ned. example if addition is performed using the bcd v alue 15 and 27, the result should be 42. the sum is incorrect, ho we v er , when the binary representations are added in the destination location using standard binary arithmetic. 0 001 0101 = 15h + 0 010 0111 = 27 h 0 011 1100 = 3c h re gister 45f contains the v alue 5fh , and the result of the addition is stored in re gister 5fh , the statement: da @45h op code: 40 45 adjusts this result so the correct bcd representation is obtained. 0011 1100 = 3ch 0000 0110 = 06h 0100 0010 = 42 h re gister 5fh no w contains the v alue 42h . the c, z, and s ? ags are cleared, and v is unde? ned.
z8 cpu user manual um001602-0904 instruction description 245 decrement dec dst instruction format operation dst dst? the contents of the destination operand are decremented by one. address modes r or ir can be used to specify a 4-bit w orking re gister . in this format, the destination w orking re gister operand is speci? ed by add - ing 1110b ( eh ) to the high nibble of the operand. f or e xample, if w orking re gister r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example if w orking re gister r10 contains 2a%, the statement: dec r10 op code: 00 ea cycles opc (hex) address mode dst opc dst 6 00 r 6 01 ir flag description c unaf fected z set if the result is zero; cleared otherwise s set if the result of bit 7 is set (negative); cleared otherwise v set if arithmetic overflow occurs; cleared otherwise d unaf fected h unaf fected e dst note:
z8 family of microcontrollers user manual instruction description um001602-0904 246 lea v es the v alue 29h in w orking re gister r10. the z, v , and s ? ags are cleared. example if re gister b3h contains cbh , and re gister cbh contains 01h , the state - ment: dec @b3h op code: 01 b3 lea v es the v alue 00h in re gister cbh . the z flag is set, and the v and s ? ags are cleared.
z8 cpu user manual um001602-0904 instruction description 247 decrement and jump if non-zero djnz r, dst instruction format operation r r?; if r <> 0, pc pc + dst the speci? ed w orking re gister being used as a counter is decremented. if the contents of the speci? ed w orking re gister are not zero after decre - menting, then the relati v e address is added to the program counter (pc) and control passes to the statement whose address is no w in the pc. the range of the relati v e address is +127 to C128. the original v alue of the pc is the address of the instruction byte follo wing the djnz statement. when the speci? ed w orking re gister counter reaches zero, control f alls through to the statement follo wing the djnz instruction. the w orking re gister being used as a counter must be one of the re gisters from 04h to efh . use of one of the i/o ports, control or peripheral re gis - ters will ha v e unde? ned results. cycles opc (hex) address mode dst r opc dst 12 if jump taken ra r 10 if jump not taken (r = 0 to f) r flag description c unaf fected z unaf fected s unaf fected v unaf fected d unaf fected h unaf fected note:
z8 family of microcontrollers user manual instruction description um001602-0904 248 example djnz is typically used to control a loop of instructions. in this e xample, 12 bytes are mo v ed from one b uf fer area in the re gister ? le to another . the steps in v olv ed are: ? load 12 into the counter (w orking re gister r6) ? set up the loop to perform the mo v es ? end the loop with djnz the assembly listing required for this routine is as follo ws: ld r6, 12 ;load counter loop: ld r9, @r6 ;move one byte to ld @r6, r9 ;new location djnz r6, loop ;decrement and loop until counter ;= 0
z8 cpu user manual um001602-0904 instruction description 249 decrement w ord decw dst instruction format operation dst dst? the contents of the destination (which must be an e v en address) operand are decremented by one. the destination operand can be a re gister p air or a w orking re gister p air . address modes rr or ir can be used to specify a 4-bit w orking re gister p air . in this format, the destination w orking re gister p air operand is spec - i? ed by adding 1110b ( eh ) to the high nibble of the operand. f or e xample, if w orking re gister p air r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example if re gister p air 30h and 31h contain the v alue 0af2h , the statement: cycles opc (hex) address mode dst opc dst 10 80 rr 10 81 ir flag description c unaf fected z set if the result is zero; cleared otherwise s set if the result of bit 7 is set (negative); cleared otherwise v set if arithmetic overflow occurs; cleared otherwise d unaf fected h unaf fected e dst note:
z8 family of microcontrollers user manual instruction description um001602-0904 250 decw 30h op code: 80 30 lea v es the v alue 0af1h in re gister p air 30h and 31h . the z, v , and s ? ags are cleared. example if w orking re gister r0 contains 30h and re gister p airs 30h and 31h contain the v alue faf3h , the statement: decw @r0 op code: 81 e0 lea v es the v alue faf2h in re gister p air 30h and 31h . the s flag is set, and the z and v ? ags are cleared.
z8 cpu user manual um001602-0904 instruction description 251 disable interrupts dl instruction format operation imr (7) 0 bit 7 of control re gister fbh (the interrupt mask re gister) is reset to 0. all interrupts are disabled, although the y remain potentially enabled. (f or instance, the global interrupt enable is cleared, b ut not the indi vidual interrupt le v el enables.) example if control re gister fbh contains 8ah ( 10001010 ) (interrupts irq1 and irq3 are enabled), the statement: di op code: 8f sets control re gister fbh to 0ah ( 00001010b ) and disables these inter - rupts. cycles opc (hex) opc 6 8f flag description c unaf fected z unaf fected s unaf fected v unaf fected d unaf fected h unaf fected
z8 family of microcontrollers user manual instruction description um001602-0904 252 enable interrupts ei instruction format operation imr (7) 0 bit 7 of control re gister fbh (the interrupt mask re gister) is set to 1. this allo ws potentially enabled interrupts to become enabled. example if control re gister fbh contains 0ah ( 00001010 ) (interrupts irq1 and irq3 are selected), the statement: ei op code: 9f sets control re gister fbh to 8ah ( 10001010b ) and enables irq1 and irq3. cycles opc (hex) opc 6 9f flag description c unaf fected z unaf fected s unaf fected v unaf fected d unaf fected h unaf fected
z8 cpu user manual um001602-0904 instruction description 253 halt halt instruction format operation the hal t instruction turns of f the internal cpu clock, b ut not the xt al oscillation. the counter/timers and the e xternal interrupts irq1, irq2, and irq3 remain acti v e. the de vices are reco v ered by interrupts, either e xternally or internally generated. in order to enter hal t mode, it is necessary to ? rst ? ush the instruction pipeline to a v oid suspending e x ecution in mid-instruction. the user must e x ecute a nop immediately before the e x ecution of the hal t instruction. example assuming the z8 ? cpu is in normal operation, the statements: nop halt op codes: ff 7f place the z8 ? cpu into hal t mode. cycles opc (hex) opc 6 7f flag description c unaf fected z unaf fected s unaf fected v unaf fected d unaf fected h unaf fected note:
z8 family of microcontrollers user manual instruction description um001602-0904 254 increment instruction format operation dst dst + 1 the contents of the destination operand are incremented by one. address modes r or ir can be used to specify a 4-bit w orking re gister . in this format, the destination w orking re gister operand is speci? ed by add - ing 1110b ( eh ) to the high nibble of the operand. f or e xample, if w orking re gister r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example if w orking re gister r10 contains 2ah , the statement: cycles opc (hex) address mode dst dst opc 6 re r opc dst 6 20 r 6 21 ir flag description c unaf fected z set if the result is zero; cleared otherwise. s set if the result of bit 7 is set (negative); cleared otherwise. v set if arithmetic overflow occurs; cleared otherwise. d unaf fected h unaf fected e dst note:
z8 cpu user manual um001602-0904 instruction description 255 inc r10 op code: ae lea v es the v alue 2bh in w orking re gister r10. the z, v , and s ? ags are cleared. example if re gister b3h contains cbh , the statement: inc b3h op code: 20 b3 lea v es the v alue cch in re gister cbh . the s flag is set, and the z and v ? ags are cleared. example if re gister b3h contains cbh and re gister bch contains ffh , the state - ment: inc @b3h op code: 21 b3 lea v es the v alue 00h in re gister cbh . the z flag is set, and the v and s ? ags are cleared.
z8 family of microcontrollers user manual instruction description um001602-0904 256 increment w ord incw dst instruction format operation dst dst? the contents of the destination (which must be an e v en address) operand is decremented by one. the destination operand can be a re gister p air or a w orking re gister p air . address modes rr or ir can be used to specify a 4-bit w orking re gister p air . in this format, the destination w orking re gister p air operand is spec - i? ed by adding 1110b ( eh ) to the high nibble of the operand. f or e xam - ple, if w orking re gister p air r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code example if re gister p airs 30h and 31h contain the v alue 0af2h , the statement: cycles opc (hex) address mode dst opc dst 10 a0 rr 10 a1 ir 10 a0 r flag description c unaf fected z set if the result is zero; cleared otherwise. s set if the result of bit 7 is set (negative); cleared otherwise. v set if arithmetic overflow occurs; cleared otherwise. d unaf fected h unaf fected e dst note:
z8 cpu user manual um001602-0904 instruction description 257 incw 30h op code: a0 30 lea v es the v alue 0af3h in re gister p air 30h and 31h . the z, v , and s ? ags are cleared. example if w orking re gister r0 contains 30h , and re gister p airs 30h and 31h contain the v alue faf3h , the statement: incw @r0 op code: a1 e0 lea v es the v alue faf4h in re gister p air 30h and 31h . the s flag is set, and the z and v ? ags are cleared.
z8 family of microcontrollers user manual instruction description um001602-0904 258 interrupt return iret instruction format operation flags @sp sp sp + 1 pc @sp sp sp + 2 imr (7) 1 this instruction is issued at the end of an interrupt service routine. it restores the flag re gister (control re gister fch ) and the pc. it also re- enables an y interrupts that are potentially enabled. example if stack pointer lo w re gister ffh currently contains the v alue 45h , re g - ister 45h c ontains the v alue 00h , re gister 46h contains 6fh , and re gister 47 contains e4h , the statement: iret op code: bf cycles opc (hex) opc 16 8f flag description c restored to original setting before the interrupt occurred. z restored to original setting before the interrupt occurred. s restored to original setting before the interrupt occurred. v restored to original setting before the interrupt occurred. d restored to original setting before the interrupt occurred. h restored to original setting before the interrupt occurred.
z8 cpu user manual um001602-0904 instruction description 259 restores the fla g re gister fch with the v alue 00h , restores the pc with the v alue 6fe4h, re-enables the interrupts, and sets the stack pointer lo w to 48h. the ne xt instruction to be e x ecuted will be at location 6fe4h.
z8 family of microcontrollers user manual instruction description um001602-0904 260 jump jp cc, dst instruction format operation if cc (condition code) is true, then pc dst a conditional jump transfers program control to the destination address if the condition speci? ed by cc (condition code) is true. otherwise, the instruction follo wing the jp instruction is e x ecuted. see section 12.3 for a list of condition codes. the unconditional jump simply replaces the contents of the program counter with the contents of the re gister pair speci? ed by the destination operand. program control then passes to the instruction addressed by the pc. address mode irr can be used to specify a 4-bit w orking re gister . in this format, the destination w orking re gister operand is speci? ed by adding 1110b ( eh ) to the high nibble of the operand. f or e xample, if w orking cycles opc (hex) address mode dst cc opc dst 12 if jump taken ccd da 10 if jump not taken cc = 0 to f dst dst 8 30 irr flag description c unaf fected z unaf fected s unaf fected v unaf fected d unaf fected h unaf fected note:
z8 cpu user manual um001602-0904 instruction description 261 re gister r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example if the carry flag is set, the statement: jp c, 1520h op code: 7d 15 20 replaces the contents of the program counter with 1520h and transfers program control to that location. if the carry flag had not been set, con - trol w ould ha v e f allen through to the statement follo wing the jp instruc - tion. example if w orking re gister p air rr2 contains the v alue 3f45h , the statement: jp @rr2 op code: 30 e2 replaces the contents of the pc with the v alue 3f45h and transfers pro - gram control to that location. e dst
z8 family of microcontrollers user manual instruction description um001602-0904 262 jump relative jr cc, dst instruction format operation if cc is true, pc pc + dst if the condition speci? ed by the cc is true, the relati v e address is added to the pc and control passes to the instruction located at the address speci - ? ed by the pc (see section 12.3 for a list of condition codes). otherwise, the instruction follo wing the jr instruction is e x ecuted. the range of the relati v e address is +127 to C128, and the original v alue of the pc is tak en to be the address of the ? rst instruction byte follo wing the jr instruction. example if the result of the last arithmetic operation e x ecuted is ne g ati v e, the ne xt four statements (which occup y a total of se v en bytes) are skipped with the statement: jr ml, #9 op code: 5b 09 cycles opc (hex) address mode dst cc opc dst 12 if jump taken ccb rr 10 if jump not taken cc = 0 to f flag description c unaf fected z unaf fected s unaf fected v unaf fected d unaf fected h unaf fected
z8 cpu user manual um001602-0904 instruction description 263 if the result w as not ne g ati v e, e x ecution w ould ha v e continued with the instruction follo wing the jr instruction. example a short form of a jump C45 is: jr #?5 op code: 8b d3 the condition code is blank in this case, and is assumed to be always true .
z8 family of microcontrollers user manual instruction description um001602-0904 264 load ld dst, src instruction format operation dst src the contents of the source operand are loaded into the destination oper - and. the contents of the source operand are not af fected. cycles opc (hex) address mode d st s rc dst opc src 6 rc r im 6 r8 r r src opc dst 6 r9 r* r r = 0 to f opc dst opc 6 e3 r ir 6 f3 ir r opc src dst 10 e4 r r 10 e5 r ir opc dst src 10 e6 r im 10 e7 ir im opc src dst 10 f5 ir r opc dst x src 10 c7 r x opc src x dst 10 d7 x r
z8 cpu user manual um001602-0904 instruction description 265 address modes r or ir can be used to specify a 4-bit w orking re gister . in this format, the source or destination w orking re gister operand is speci - ? ed by adding 1110b ( eh ) to the high nibble of the operand. f or e xample, if w orking re gister r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example the statement: ld r15, # 34h op code: fc 34 loads the v alue 34h into w orking re gister r15. example if re gister 34h contains the v alue fch , the statement: ld r14, 34h op code: f8 34 loads the v alue fch into w orking re gister r15. the contents of re gister 34h are not af fected. example if w orking re gister r14 contains the v alue 45h , the statement: flag description c unaf fected z unaf fected s unaf fected v unaf fected d unaf fected h unaf fected e src or e dst note:
z8 family of microcontrollers user manual instruction description um001602-0904 266 ld 34h , r14 op code: e9 34 loads the v alue 45h into re gister 34h . the contents of w orking re gister r14 are not af fected. example if w orking re gister r12 contains the v alue 34h , and re gister 34h con - tains the v alue ffh , the statement: ld r13, @r12 op code: e3 dc loads the v alue ffh into w orking re gister r13. the contents of w orking re gister r12 and re gister r34 are not af fected. example if w orking re gister r13 contains the v alue 45h , and w orking re gister r12 contains the v alue 00h the statement: ld @r13, r12 op code: f3 dc loads the v alue 00h into re gister 45h . the contents of w orking re gister r12 and w orking re gister r13 are not af fected. example if re gister 45h contains the v alue cfh , the statement: ld 34h , 45h op code: e4 45 34 loads the v alue cfh i nto re gister 34h . the contents of re gister 45h are not af fected. example if re gister 45h contains the v alue cfh a nd re gister cfh contains the v alue ffh , the statement:
z8 cpu user manual um001602-0904 instruction description 267 ld 34h , @45h op code: e5 45 34 loads the v alue ffh into re gister 34h . the contents of re gister 45h and re gister cfh a re not af fected. example the statement: ld 34h , #a4h op code: e6 34 a4 loads the v alue a4h into re gister 34h . example if w orking re gister r14 contains the v alue 7fh , the statement: ld @r14, # fch op code: e7 ee fc loads the v alue fch into re gister 7fh . the contents of w orking re gister r14 are not af fected. example if re gister 34h contains the v alue cfh a nd re gister 45h contains the v alue ffh , the statement: ld @ 34h , 45h op code: f5 45 34 loads the v alue ffh into re gister cfh . the contents of re gister 34h and re gister 45h are not af fected. example iif w orking re gister r0 contains the v alue 08h and re gister 2ch ( 24h + 08h = 2ch ) contains the v alue 4fh , the statement: ld r10, 24h (r0) op code: c7 a0 24
z8 family of microcontrollers user manual instruction description um001602-0904 268 loads w orking re gister r10 with the v alue 4fh . the contents of w orking re gister r0 and re gister 2ch are not af fected. example if w orking re gister r0 contains the v alue 0bh and w orking re gister r10 contains 83h the statement: ld f0h(r0), r10 op code: d7 a0 f0 loads the v alue 83h into re gister fbh ( f0h + 0bh = fbh ). because this is the interrupt mask re gister , the lo ad statement has the ef fect of enabling irq0 and irq1. the contents of w orking re gisters r0 and r10 are unaf fected by the load.
z8 cpu user manual um001602-0904 instruction description 269 load constant ldc dst, src instruction format operation dst src this instruction is used to load a byte constant from program memory into a w orking re gister , or vice v ersa. the address of the program mem - ory location is speci? ed by a w orking re gister p air . the contents of the source operand are not af fected. example if w orking re gister p air r6 and r7 contain the v alue 30a2h a nd program memory location 30a2h contains the v alue 22h , the statement: ldc r2, @rr6 op code: c2 26 cycles opc (hex) address mode d st s rc opc dst src 12 c2 r irr opc dst src 12 d2 irr r flag description c unaf fected z unaf fected s unaf fected v unaf fected d unaf fected h unaf fected
z8 family of microcontrollers user manual instruction description um001602-0904 270 loads the v alue 22h into w orking re gister r2. the v alue of program memory location 30a2h is unchanged by the load. example if w orking re gister r2 contains the v alue 22h , and w orking re gister p air r6 and r7 contains the v alue 10a2h , the statement: ldc @rr6, r2 op code: d2 26 loads the v alue 22h into program memory location 10a2h . the v alue of w orking re gister r2 is unchanged by the load. this instruction format is v alid only for mcus which can address e xternal program memory . note:
z8 cpu user manual um001602-0904 instruction description 271 load constant autoincrement ldci dst, src instruction format operation dst src r r + 1 rr rr + 1 this instruction is used for block transfers of data between program mem - ory and the re gister file. the address of the program memory location is speci? ed by a w orking re gister p air , and the address of the re gister file location is speci? ed by w orking re gister . the contents of the source loca - tion are loaded into the destination location. both addresses in the w ork - ing re gisters are then incremented automatically . the contents of the source operand are not af fected. cycles opc (hex) address mode d st s rc opc dst src 18 c3 ir irr opc dst src 18 d3 irr ir flag description c unaf fected z unaf fected s unaf fected v unaf fected d unaf fected h unaf fected
z8 family of microcontrollers user manual instruction description um001602-0904 272 example if w orking re gister p air r6Cr7 contains 30a2h , program memory loca - tion 30a2h and 30a3h contain 22h and bch respecti v ely , and w orking re gister r2 contains 20h , the statement: ldci @r2, @rr6 op code: c3 26 loads the v alue 22h into re gister 20h . w orking re gister p air rr6 is incremented to 30a3h and w orking re gister r2 is incremented to 21h . a second ldci @r2, @rr6 op code: c3 26 loads the v alue bch into re gister 21h . w orking re gister p air rr6 is incremented to 30a4h and w orking re gister r2 is incremented to 22h . example if w orking re gister r2 contains 20h , re gister 20h contains 22h , re gis - ter 21h c ontains bch , and w orking re gister p air r6Cr7 contains 30a2h , the statement: ldci @rr6, @r2 op code: d3 26 loads the v alue 22h into program memory location 30a2h . w orking re g - ister r2 is incremented to 21h a nd w orking re gister p air r6Cr7 is incre - mented to 30a3h . a second ldci @rr6, @r2 op code: d3 26 loads the v alue bch into program memory location 30a3h . w orking re g - ister r2 is incremented to 22h a nd w orking re gister p air r6Cr7 is incre - mented to 30a4h .
z8 cpu user manual um001602-0904 instruction description 273 load external data lde dst, src instruction format operation dst src this instruction is used to load a byte from e xternal data memory into a w orking re gister or vice v ersa. the address of the e xternal data memory location is speci? ed by a w orking re gister p air . the contents of the source operand are not af fected. example if w orking re gister p air r6 and r7 contain the v alue 40a2h a nd e xternal data memory location 40a2h contains the v alue 22h , the statement: lde r2, @rr6 op code: 82 26 cycles opc (hex) address mode d st s rc opc dst src 12 82 r irr opc src dst 12 92 irr r flag description c unaf fected z unaf fected s unaf fected v unaf fected d unaf fected h unaf fected
z8 family of microcontrollers user manual instruction description um001602-0904 274 loads the v alue 22h into w orking re gister r2. the v alue of e xternal data memory location 40a2h is unchanged by the load. example if w orking re gister p air r6 and r7 contain the v alue 404ah and w orking re gister r2 contains the v alue 22h , the statement: lde @rr6, r2 op code: 92 26 loads the v alue 22h into e xternal data memory location 404ah this instruction format is v alid only for mcus which can address e xternal data memory . note:
z8 cpu user manual um001602-0904 instruction description 275 load external data autoincrement ldei dst, src instruction format operation dst src r r + 1 rr rr + 1 this instruction is used for block transfers of data between e xternal data memory and the re gister file. the address of the e xternal data memory location is speci? ed by a w orking re gister p air , and the address of the re gister file location is speci? ed by a w orking re gister . the contents of the source location are loaded into the destination location. both addresses in the w orking re gisters are then incremented automatically . the contents of the source are not af fected. cycles opc (hex) address mode d st s rc opc dst src 18 83 ir irr opc src dst 18 93 irr ir flag description c unaf fected z unaf fected s unaf fected v unaf fected d unaf fected h unaf fected
z8 family of microcontrollers user manual instruction description um001602-0904 276 example if w orking re gister p air r6 and r7 contains 404ah , e xternal data mem - ory location 404ah and 40 4bh contain abh and c3h respecti v ely , and w orking re gister r2 contains 22h , the statement: ldei @r2, @rr6 op code: 83 26 loads the v alue abh into re gister 22h . w orking re gister p air rr6 is incremented to 40 4bh a nd w orking re gister r2 is incremented to 23h . a second ldei @r2, @rr6 op code: 83 26 loads the v alue c3h into re gister 23h . w orking re gister p air rr6 is incremented to 404ch and w orking re gister r2 is incremented to 24h . example if w orking re gister r2 contains 22h , re gister 22h contains abh , re gis - ter 23h contains c3h , and w orking re gister p air r6 and r7 contains 404ah , the statement: ldei @rr6, @r2 op code: 93 26 loads the v alue abh into e xternal data memory location 404ah . w orking re gister r2 is incremented to 23h and w orking re gister p air rr6 is incremented to 40 4bh . a second ldei @rr6, @r2 op code: 93 26 loads the v alue c3h into e xternal data memory location 404bh . w orking re gister r2 is incremented to 24h and w orking re gister p air rr6 is incremented to 404ch . this instruction format is v alid only for mcus which can address e xternal data memory . note:
z8 cpu user manual um001602-0904 instruction description 277 no operation nop instruction format operation no action is performed by this instruction. it is typically used for timing delays or clearing the pipeline. cycles opc (hex) opc 6 ff flag description c unaf fected z unaf fected s unaf fected v unaf fected d unaf fected h unaf fected
z8 family of microcontrollers user manual instruction description um001602-0904 278 logical and and dst, src instruction format operation dst dst and src the source operand is logically anded with the destination operand. the and operation results in a 1 being stored whene v er the corresponding bits in the tw o operands are both 1, otherwise a 0 is stored. the result is stored in the destination operand. the contents of the source bit are not af fected. address modes r or ir can be used to specify a 4-bit w orking re gister . in this format, the source or destination w orking re gister operand is speci - cycles opc (hex) address mode d st s rc opc dst src 6 42 r r 6 43 r lr opc src dst 10 44 r r 10 45 r ir opc dst src 10 46 r im 10 47 ir im flag description c unaf fected z set if the result is zero; cleared otherwise s set if the result of bit 7 is set; cleared otherwise v always reset to 0 d unaf fected h unaf fected note:
z8 cpu user manual um001602-0904 instruction description 279 ? ed by adding 1110b ( eh ) to the high nibble of the operand. f or e xample, if w orking re gister r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example if w orking re gister r1 contains 34h ( 00111000b ) and w orking re gister r14 contains 4dh ( 10001101 ), the statement: and r1, r14 op code: 52 1e example if w orking re gister r4 contains f9h ( 11111001b ), w orking re gister r13 contains 7bh , and re gister 7bh contains 6ah ( 01101010b ), the statement: and r4, @r13 op code: 53 4d lea v es the v alue 68h ( 01101000b ) in w orking re gister r4. the z, v , and s ? ags are cleared. example if re gister 3ah contains the v alue f5h ( 11110101b ) and re gister 42h contains the v alue 0ah ( 00001010 ), the statement: and 3ah, 42h op code: 54 42 3a lea v es the v alue 00h ( 00000000b ) in re gister 3ah . the z flag is set, and the v and s ? ags are cleared. example if w orking re gister r5 contains f0h ( 11110000b ), re gister 45h con - tains 3ah , and re gister 3ah contains 7fh ( 01111111b ), the statement: e src or e dst
z8 family of microcontrollers user manual instruction description um001602-0904 280 and r5, @45h op code: 55 45 e5 lea v es the v alue 70h ( 01110000b ) in w orking re gister r5. the z, v , and s ? ags are cleared. example if re gister 7ah contains the v alue f7h ( 11110111b ), the statement: and 7ah, #f0h op code: 56 7a f0 lea v es the v alue f0h ( 11110000b ) in re gister 7ah . the s flag is set, and the z and v ? ags are cleared. example if w orking re gister r3 contains the v alue 3eh a nd re gister 3eh contains the v alue ech ( 11101100b ), the statement: and @r3, #05h op code: 57 e3 05 lea v es the v alue 04h ( 00000100b ) in re gister 3eh . the z, v , and s ? ags are cleared.
z8 cpu user manual um001602-0904 instruction description 281 logical or or dst, src instruction format operation dst dst or src the source operand is logically ored with the destination operand and the result is stored in the destination operand. the contents of the source operand are not af fected. the or operation results in a one bit being stored whene v er either of the corresponding bits in the tw o operands is a one. otherwise, a zero bit is stored. address modes r or ir can be used to specify a 4-bit w orking re gister . in this format, the source or destination w orking re gister operand is speci - cycles opc (hex) address mode d st s rc opc dst src 6 02 r r 6 03 r lr opc src dst 10 04 r r 10 05 r ir opc dst src 10 06 r im 10 07 ir im flag description c unaf fected z set if the result is zero; cleared otherwise s set if the result of bit 7 is set; cleared otherwise v always reset to 0 d unaf fected h unaf fected note:
z8 family of microcontrollers user manual instruction description um001602-0904 282 ? ed by adding 1110b ( eh ) to the high nibble of the operand. f or e xample, if w orking re gister r12 ( ch ) is the destination operand, then ech will be used as the destination operand in the op code. example if w orking re gister r1 contains 34h ( 00111000b ) and w orking re gister r14 contains 4dh ( 10001101 ), the statement: or r1, r14 op code: 42 1e lea v es the v alue bdh ( 10111101b ) in w orking re gister r1. the s flag is set, and the z and v ? ags are cleared. example if w orking re gister r4 contains f9h ( 11111001b ), w orking re gister r13 contains 7bh , and re gister 7b contains 6ah ( 01101010b ), the state - ment: or r4, @r13 op code: 43 4d lea v es the v alue fbh ( 11111011b ) in w orking re gister r4. the s flag is set, and the z and v ? ags are cleared. example if re gister 3ah contains the v alue f5h ( 11110101b ) and re gister 42h contains the v alue 0ah ( 00001010 ), the statement: or 3ah, 42h op code: 44 42 3a lea v es the v alue ffh ( 11111111b ) in re gister 3ah . the s flag is set, and the z and v ? ags are cleared. e src or e dst
z8 cpu user manual um001602-0904 instruction description 283 example if w orking re gister r5 contains 70h ( 01110000b ), re gister 45h con - tains 3ah , and re gister 3ah contains 7fh ( 01111111b ), the statement: or r5, @45h op code: 45 45 e5 lea v es the v alue 7fh ( 01111111b ) in w orking re gister r5. the z, v , and s ? ags are cleared. example if re gister 7ah contains the v alue f3h ( 11110111b ), the statement: or 7ah, #f0h op code: 46 7a f0 lea v es the v alue f3h ( 11110111b ) in re gister 7ah . the s flag is set, and the z and v ? ags are cleared. example if w orking re gister r3 contains the v alue 3eh a nd re gister 3eh c ontains the v alue 0ch ( 00001100b ), the statement: or @r3, #05h op code: 57 e3 05 lea v es the v alue 0dh ( 00001101b ) in re gister 3eh . the z, v , and s ? ags are cleared.
z8 family of microcontrollers user manual instruction description um001602-0904 284 logical exclusive or xor dst, src instruction format operation dst dst xor src the source operand is logically exclusive ored with the destination operand. the xor operation results in a 1 being stored in the destination operand whene v er the corresponding bits in the tw o operands are dif fer - ent, otherwise a 0 is stored. the contents of the source operand are not af fected. address modes r or ir can be used to specify a 4-bit w orking re gister . in this format, the source or destination w orking re gister operand is speci - ? ed by adding 1110b ( eh ) to the high nibble of the operand. f or e xample, cycles opc (hex) address mode d st s rc opc dst src 6 82 r r 6 83 r lr opc src dst 10 84 r r 10 85 r ir opc dst src 10 86 r im 10 87 ir im c unaf fected z set if the result is zero; cleared otherwise. s set if the result of bit 7 is set; cleared otherwise. v always reset to 0 d unaf fected h unaf fected note:
z8 cpu user manual um001602-0904 instruction description 285 if w orking re gister r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example if w orking re gister r1 contains 34h ( 00111000b ) and w orking re gister r14 contains 4dh ( 10001101b ), the statement: xor r1, r14 op code: b2 1e lea v es the v alue bdh ( 10111101b ) in w orking re gister r1. the z, and v ? ags are cleared, and the s flag is set. example if w orking re gister r4 contains f9h ( 11111001b ), w orking re gister r13 contains 7bh , and re gister 7bh contains 6ah ( 01101010b ), the statement: xor r4, @r13 op code: b3 4d lea v es the v alue 93h ( 10010011b ) in w orking re gister r4. the s flag is set, and the z, and v ? ags are cleared. example if re gister 3ah contains the v alue f5h ( 11110101b ) and re gister 42h contains the v alue 0ah ( 00001010b ), the statement: xor 3ah, 42h op code: b4 42 3a lea v es the v alue ffh ( 11111111b ) in re gister 3ah . the s flag is set, and the c and v ? ags are cleared. e src or e dst
z8 family of microcontrollers user manual instruction description um001602-0904 286 example if w orking re gister r5 contains f0h ( 11110000b ), re gister 45h con - tains 3ah , and re gister 3ah contains 7fh ( 01111111b ), the statement: xor r5, @45h op code: b5 45 e5 lea v es the v alue 8fh ( 10001111b ) in w orking re gister r5. the s flag is set, and the c and v ? ags are cleared. example if re gister 7ah contains the v alue f7h ( 11110111b ), the statement: xor 7ah, #f0h op code: b6 7a f0 lea v es the v alue 07h ( 00000111b ) in re gister 7ah . the z, v and s ? ags are cleared. example if w orking re gister r3 contains the v alue 3eh a nd re gister 3eh contains the v alue 6ch ( 01101100b ), the statement: xor @r3, #05h op code: b7 e3 05 lea v es the v alue 69h ( 01101001b ) in re gister 3eh . the z, v , and s ? ags are cleared.
z8 cpu user manual um001602-0904 instruction description 287 pop pop dst instruction format operation dst @sp sp sp + 1 the contents of the location speci? ed by the sp (stack pointer) are loaded into the destination operand. the sp is then incremented automatically . address modes r or ir can be used to specify a 4-bit w orking re gister . in this format, the destination w orking re gister operand is speci? ed by add - ing 1110b ( eh ) to the high nibble of the operand. f or e xample, if w orking re gister r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. cycles opc (hex) address mode dst opc dst 10 50 r 10 51 ir flag description c unaf fected z unaf fected s unaf fected v unaf fected d unaf fected h unaf fected e dst
z8 family of microcontrollers user manual instruction description um001602-0904 288 example if the sp (control re gisters feh and ffh ) contains the v alue 70h and re gister 70h contains 44h , the statement: pop 34h op code: 50 34 loads the v alue 44h into re gister 34h . after the pop operation, the sp contains 71h . the contents of re gister 70 are not af fected. example if the sp (control re gisters feh and ffh ) contains the v alue 1000h , e xternal data memory location 1000h contains 55h , and w orking re gis - ter r6 contains 22h , the statement: pop @r6 op code: 51 e6 loads the v alue 55h into re gister 22h . after the pop operation, the sp contains 1001h . the contents of w orking re gister r6 are not af fected.
z8 cpu user manual um001602-0904 instruction description 289 push push src instruction format operation sp sp? @sp src the contents of the sp (stack pointer) are decremented by one, then the contents of the source operand are loaded into the location addressed by the decremented sp , thus adding a ne w element to the stack. address modes r or ir can be used to specify a 4-bit w orking re gister . in this format, the destination w orking re gister operand is speci? ed by add - ing 1110b ( eh ) to the high nibble of the operand. f or e xample, if w orking re gister r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. cycles opc (hex) address mode dst 10 internal stack 70 opc src 12 external stack r 10 internal stack ir 10 external stack 71 flag description c unaf fected z unaf fected s unaf fected v unaf fected d unaf fected h unaf fected e dst note:
z8 family of microcontrollers user manual instruction description um001602-0904 290 example if the sp contains 1001h , the statement: push fch op code: 70 fc stores the contents of re gister fch (the flag re gister) in location 1000h . after the push operation, the sp contains 1000h . example if the sp contains 61h and w orking re gister r4 contains fch , the state - ment: push @r4 op code: 71 e4 stores the contents of re gister fch (the flag re gister) in location 60h . after the push operation, the sp contains 60h .
z8 cpu user manual um001602-0904 instruction description 291 reset carry flag rcf instruction format operation c 0 the c flag is reset to 0, re g ardless of its pre vious v alue. example if the c flag is currently set, the statement: rcf op code: cf resets the carry flag to 0. cycles opc (hex) opc 6 cf flag description c reset to 0 z unaf fected s unaf fected v unaf fected d unaf fected h unaf fected
z8 family of microcontrollers user manual instruction description um001602-0904 292 return ret instruction format operation pc @sp sp sp + 2 this instruction is normally used to return from a procedure entered by a call instruction. the contents of the location addressed by the sp are popped into the pc. the ne xt statement e x ecuted is the one addressed by the ne w contents of the pc. the stack pointer is also incremented by tw o. each push instruction e x ecuted within the subroutine should be coun - tered with a pop instruction in order to guarantee the sp is at the correct location when the ret instruction is e x ecuted. otherwise the wrong address will be loaded into the pc and the program will not operate as appropriate . cycles opc (hex) opc 14 af flag description c unaf fected z unaf fected s unaf fected v unaf fected d unaf fected h unaf fected note:
z8 cpu user manual um001602-0904 instruction description 293 example if sp contains 2000h , e xternal data memory location 2000h contains 18h , and location 2001h contains b5h , the statement: ret op code: af lea v es the v alue 2002h in the sp , and the pc contains 18b5h , the address of the ne xt instruction to be e x ecuted.
z8 family of microcontrollers user manual instruction description um001602-0904 294 rotate left rl dst instruction format operation c dst(7) dst(0) dst(7) dst(1) dst(0) dst(2) dst(1) dst(3) dst(2) dst(4) dst(3) dst(5) dst(4) dst(6) dst(5) dst(7) dst(6) the contents of the destination operand are rotated left by one bit posi - tion. the initial v alue of bit 7 is mo v ed to the bit 0 position and also into the carry flag, as sho wn belo w . cycles opc (hex) address mode dst opc dst 6 90 r 6 91 ir cd7d6d 5d4d3d2d1d0
z8 cpu user manual um001602-0904 instruction description 295 address modes r or ir can be used to specify a 4-bit w orking re gister . in this format, the destination w orking re gister operand is speci? ed by add - ing 1110b ( eh ) to the high nibble of the operand. f or e xample, if w orking re gister r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example if the contents of re gister c6h are 88h ( 10001000b ), the statement: rl c6h op code: 80 c6 lea v es the v alue 11h ( 00010001b ) in re gister c6h . the c and v flags are set, and the s and z ? ags are cleared. example if the contents of re gister c6h are 88h , and the contents of re gister 88h are 44h ( 01000100b ), the statement: rl @c6h op code: 81 c6 lea v es the v alue 88h in re gister 88h ( 10001000b ). the s and v flags are set, and the c and z ? ags are cleared. flag description c set if the bit rotated from the most significant bit position was 1 ( i.e., bit 7 was 1). z set if the result is zero; cleared otherwise. s set if the result in bit 7 is set; cleared otherwise. v set if arithmetic overflow occurred (if the sign of the destination operand changed during rotation); cleared otherwise. d unaf fected . h unaf fected . e dst note:
z8 family of microcontrollers user manual instruction description um001602-0904 296 rotate left through carry rlc dst instruction format operation c dst(7) dst(0) c dst(1) dst(0) dst(2) dst(1) dst(3) dst(2) dst(4) dst(3) dst(5) dst(4) dst(6) dst(5) dst(7) dst(6) the contents of the destination operand along with the c flag are rotated left by one bit position. the initial v alue of bit 7 replaces the c flag and the initial v alue of the c flag replaces bit 0, as sho wn belo w . cycles opc (hex) address mode dst opc dst 6 10 r 6 1 1 ir cd7d6d 5d4d3d2d1d0
z8 cpu user manual um001602-0904 instruction description 297 address modes r or ir can be used to specify a 4-bit w orking re gister . in this format, the destination w orking re gister operand is speci? ed by add - ing 1110b ( eh ) to the high nibble of the operand. f or e xample, if w orking re gister r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example if the c flag is reset and re gister c6 contains 8fh ( 10001111b ), the statement: rlc c6 op code: 10 c6 lea v es re gister c6 with the v alue 1eh ( 00011110b ). the c and v flags are set, and s and z ? ags are cleared. example if the c flag is reset, w orking re gister r4 contains c6h , and re gister c6 contains 8fh ( 10001111b ), the statement: rlc @r4 op code: 11 e4 lea v es re gister c6 with the v alue 1eh ( 00011110b ). the c and v flags are set, and s and z ? ags are cleared. flag description c set if the bit rotated from the most significant bit position was 1 (i.e., bit 7 was 1). z set if the result is zero; cleared otherwise. s set if the result bit 7 is set; cleared otherwise. v set if arithmetic overflow occurred (if the sign of the destination operand changed during rotation); cleared otherwise. d unaf fected h unaf fected e dst note:
z8 family of microcontrollers user manual instruction description um001602-0904 298 rotate right rr dst instruction format operation c dst(0) dst(0) dst(1) dst(1) dst(2) dst(2) dst(3) dst(3) dst(4) dst(4) dst(5) dst(5) dst(6) dst(6) dst(7) dst(7) dst(0) the contents of the destination operand are rotated to the right by one bit position. the initial v alue of bit 0 is mo v ed to bit 7 and also into the c flag, as sho wn belo w . cycles opc (hex) address mode dst opc dst 6 e0 r 6 e1 ir c d7 d6 d5 d4 d3 d2 d1 d0
z8 cpu user manual um001602-0904 instruction description 299 address modes r or ir can be used to specify a 4-bit w orking re gister . in this format, the destination w orking re gister operand is speci? ed by add - ing 1110b ( eh ) to the high nibble of the operand. f or e xample, if w orking re gister r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example if the contents of w orking re gister r6 are 31h (00110001b), the state - ment: rr r6 op code: e0 e6 lea v es the v alue 98h ( 10011000 ) in w orking re gister r6. the c, v , and s flags are set, and the z flag is cleared. example if the contents of re gister c6 are 31h and the contents of re gister 31h are 7eh ( 01111110b ), the statement: rr @c6 op code: e1 c6 lea v es the v alue 4fh ( 00111111 ) in re gister 31h . the c, z, v , and s ? ags are cleared. flag description c set if the bit rotated from the least significant bit position was 1 ( i.e., bit 0 was 1). z set if the result is zero; cleared otherwise. s set if the result bit 7 is set; cleared otherwise. v set if arithmetic overflow occurred (if the sign of the destination operand changed during rotation); cleared otherwise. d unaf fected h unaf fected e dst note:
z8 family of microcontrollers user manual instruction description um001602-0904 300 rotate right through carry rrc dst instruction format operation c dst(0) dst(0) dst(1) dst(1) dst(2) dst(2) dst(3) dst(3) dst(4) dst(4) dst(5) dst(5) dst(6) dst(6) dst(7) dst(7) c the contents of the destination operand with the c flag are rotated right by one bit position. the initial v alue of bit 0 replaces the c flag and the initial v alue of the c flag replaces bit 7, as sho wn belo w . cycles opc (hex) address mode dst opc dst 6 c0 r 6 c1 ir c d7 d6 d5 d4 d3 d2 d1 d0
z8 cpu user manual um001602-0904 instruction description 301 address modes r or ir can be used to specify a 4-bit w orking re gister . in this format, the destination w orking re gister operand is speci? ed by add - ing 1110b ( eh ) to the high nibble of the operand. f or e xample, if w orking re gister r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example if the contents of re gister c6h are ddh ( 11011101b ) and the c flag is reset, the statement: rrc c6h op code: c0 c6 lea v es the v alue 6eh ( 01101110b ) in re gister c6h . the c and v flags are set, and the z and s ? ags are cleared. example if the contents of re gister 2ch are edh , the contents of re gister edh is ( 00000000b ), and the c flag is reset, the statement: rrc @ 2ch op code: c1 2c lea v es the v alue 02h ( 00000010b ) in re gister edh . the c, z, s, and v flags are reset. flag description c set if the bit rotated from the least significant bit position was 1 (i.e., bit 0 was 1). z set if the result is zero; cleared otherwise. s set if the result bit 7 is set; cleared otherwise. v set if arithmetic overflow occurred (if the sign of the destination operand changed during rotation); cleared otherwise. d unaf fected h unaf fected e dst note:
z8 family of microcontrollers user manual instruction description um001602-0904 302 set carry flag src instruction format operation c 1 the c flag is set to 1, re g ardless of its pre vious v alue. example if the c flag is currently reset, the statement: scf op code: df sets the carry flag to 1. cycles opc (hex) opc 6 df flag description c set to 1 z unaf fected s unaf fected v unaf fected d unaf fected h unaf fected
z8 cpu user manual um001602-0904 instruction description 303 set register pointer srp src instruction format operation rp src the speci? ed v alue is loaded into the re gister pointer (rp) (control re g - ister fdh ). bits 7-4 determine the w orking re gister group. bits 3-0 selects the expanded re gister bank. addressing of un-implemented w orking re gister group, while using expanded re gister banks, will point to bank 0. example srp td addresses w orking re gister group 7 of bank 0. cycles opc (hex) address mode dst opc src 6 31 im register pointe r ( fdh) w orkin g r egister group actua l r egisters contents (bin) (hex) (hex) 1 1 1 1 0000 f f0 Cf f 1 1 10 0000 e e0 Ce f 1 101 0000 d d0 Cd f 1 100 0000 c c0 Cc f 101 1 0000 b b0 Cb f 1010 0000 a a0 Ca f 1001 0000 9 90 C9 f
z8 family of microcontrollers user manual instruction description um001602-0904 304 1000 0000 8 80 C8 f 01 1 1 0000 7 70 C7 f 01 10 0000 6 60 C6 f 0101 0000 5 50 C5 f 0100 0000 4 40 C4 f 001 1 0000 3 30 C3 f 0010 0000 2 20 C2 f 0001 0000 1 10 C1 f 0000 0000 0 00 C0 f register pointe r ( fdh ) c ontents (hex) expande d r egister ban k ( hex) xxxx 1 1 1 1 f xxxx 1 1 10 e xxxx 1 101 d xxxx 1 100 c xxxx 101 1 b xxxx 1010 a xxxx 1001 9 xxxx 1000 8 xxxx 01 1 1 7 xxxx 01 10 6 xxxx 0101 5 xxxx 0100 4 xxxx 001 1 3 xxxx 0010 2 register pointe r ( fdh) w orkin g r egister group actua l r egisters contents (bin) (hex) (hex)
z8 cpu user manual um001602-0904 instruction description 305 when an expanded re gister bank , other than bank 0 is selected, access to the z8 ? standard re gister file is possible e xcept for the port re gister and general purpose re gisters 04h to 0fh . fpr register addresses 0h to fh example the statement: srp f0h op code: 31 f0 sets the re gister pointer to access e xpanded re gister bank 0 and w orking re gister group f in the z8 ? standard re gister file. all references to w orking re gisters no w af fect this group of 16 re gisters. re gisters f0h to ffh can be accessed as w orking re gisters r0 to r15. example the statement : srp 0fh op code: 31 0f xxxx 0001 1 xxxx 0000 0 flag description c unaf fected z unaf fected s unaf fected v unaf fected d unaf fected h unaf fected register pointe r ( fdh ) c ontents (hex) expande d r egister ban k ( hex) note:
z8 family of microcontrollers user manual instruction description um001602-0904 306 sets the re gister pointer to access expanded re gister bank f , re g to re g 0fh , as the current w orking re gisters. all references to w orking re gisters no w af fect this group of 16 re gisters. these re gisters are no w accessed as w orking re gisters r0 to r15. port re gisters are no w not accessable. example assume the rp currently addresses the control and peripheral w orking re gister group and the program has just entered an interrupt service rou - tine. the statement: srp 70h op code: 31 70 retains the contents of the control and peripheral re gisters by setting the rp to 70h ( 01110000b ). an y reference to w orking re gisters in the inter - rupt routine will point to re gisters 70h to 7fh .
z8 cpu user manual um001602-0904 instruction description 307 shift right arithmetic sra dst instruction format operation c dst(0) dst(0) dst(1) dst(1) dst(2) dst(2) dst(3) dst(3) dst(4) dst(4) dst(5) dst(5) dst(6) dst(6) dst(7) dst(7) dst(7) an arithmetic shift right by one bit position is performed on the destina - tion operand. bit 0 replaces the c flag. bit 7 (the sign bit) is unchanged and its v alue is shifted into bit 6, as sho wn belo w . cycles opc (hex) address mode dst opc dst 6 d0 r 6 d1 ir c d7 d6 d5 d4 d3 d2 d1 d0
z8 family of microcontrollers user manual instruction description um001602-0904 308 address modes r or ir can be used to specify a 4-bit w orking re gister . in this format, destination w orking re gister operand is speci? ed by adding 1110b ( eh ) to the high nibble of the operand. f or e xample, if w orking re gister r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example if the contents of w orking re gister r6 are 31h (00110001b), the state - ment: sra r6 op code: d0 e6 lea v es the v alue 98h (00011000) in w orking re gister r6. the c flag is set, and the z, v , and s ? ags are cleared. example if re gister c6 contains the v alue dfh , and re gister dfh contains the v alue b8h (10111000b), the statement: sra @c6 op code: d1 c6 lea v es the v alue dch (11011100b) in re gister dfh . the c, z, and v flags are reset, and the s flag is set. flag description c set if the bit rotated from the least significant bit position was 1 (i.e., bit 0 was 1). z set if the result is zero; cleared otherwise. s set if the result bit 7 is set; cleared otherwise. v always reset to 0. d unaf fected h unaf fected e dst note:
z8 cpu user manual um001602-0904 instruction description 309 stop stop instruction format operation this instruction turns of f the internal system clock (sclk) and e xternal crystal (xt al) oscillation, and reduces the standby current. st op mode i s terminated by a reset which causes the processor to restart the appli - cation program at address 000ch . in order to enter st op mode, it is necessary to ? rst ? ush the instruction pipeline to a v oid suspending e x ecution in mid-instruction. the user must e x ecute a nop immediately before the e x ecution of the st op instruction. example the statements: nop stop op codes: ff 6f place the z8 ? cpu into st op mode. cycles opc (hex) opc 6 6f flag description c unaf fected z unaf fected s unaf fected v unaf fected d unaf fected h unaf fected note:
z8 family of microcontrollers user manual instruction description um001602-0904 310 subtract sub dst, src instruction format operation dst dst?rc the source operand is subtracted from the destination operand and the result is stored in the destination operand. the contents of the source operand are not af fected. subtraction is performed by adding the tw o s complement of the source operand to the destination operand. cycles opc (hex) address mode d st s rc opc dst src 6 22 r r 6 23 r lr opc src dst 10 24 r r 10 25 r ir opc dst src 10 26 r im 10 27 ir im flag description c cleared if there is a carry from the most significant bit of the result; set otherwise, indicating a borrow . z set if the result is 0; cleared otherwise. v set if arithmetic overflow occurred (if the operands were of opposite sign and the sign of the result is the same as the sign of the source); reset otherwise. s set if the result is negative; cleared otherwise. h cleared if there is a carry from the most significant bit of the low order four bits of the result; set otherwise indicating a borrow . d always set to 1.
z8 cpu user manual um001602-0904 instruction description 311 address modes r or ir can be used to specify a 4-bit w orking re gister . in this format, the source or destination w orking re gister operand is speci - ? ed by adding 1110b ( eh ) to the high nibble of the operand. f or e xample, if w orking re gister r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example ]if w orking re gister r3 contains 16h , and w orking re gister r11 con - tains 20h , the statement: sub r3, r11 op code: 22 3b lea v es the v alue f6h in w orking re gister r3. the c, s, and d flags are set, and the z, v , and h ? ags are cleared. example if w orking re gister r15 contains 16h , w orking re gister r10 contains 20h , and re gister 20h contains 11h , the statement: sub r16, @r10 op code: 23 fa lea v es the v alue 05h in w orking re gister r15. the d flag is set, and the c, z, s, v , and h ? ags are cleared. example if re gister 34h contains 2eh , and re gister 12h contains 1bh , the state - ment: sub 34h , 12h op code: 24 12 34 lea v es the v alue 13h in re gister 34h . the d flag is set, and the c, z, s, v , and h ? ags are cleared. e src or e dst note:
z8 family of microcontrollers user manual instruction description um001602-0904 312 example if re gister 4bh contains 82h , w orking re gister r3 contains 10h , and re gister 10h contains 01h , the statement: sub 4bh , @r3 op code: 25 e3 4b lea v es the v alue 81h in re gister 4bh . the d flag is set, and the c, z, s, v , and h ? ags are cleared. example if re gister 6ch contains 2ah , the statement: sub 6ch, #03h op code: 26 6c 03 lea v es the v alue 27h in re gister 6ch . the d flag is set, and the c, z, s, v , and h ? ags are cleared. example if re gister d4h contains 5fh , re gister 5fh contains 4ch, the statement: sub @ d4h , #02h op code: 17 d4 02 lea v es the v alue 4ah in re gister 5fh . the d flag is set, and the c, z, s, v , and h ? ags are cleared.
z8 cpu user manual um001602-0904 instruction description 313 subtract w ith carry sbc dst, src instruction format operation dst dst?rc? the source operand, along with the setting of the c flag, is subtracted from the destination operand and the result is stored in the destination operand. the contents of the source operand are not af fected. subtraction is performed by adding the tw o s complement of the source operand to the destination operand. in multiple precision arithmetic, this instruction permits the carry (borro w) from the subtraction of lo w order operands to be subtracted from the subtraction of high order operands. cycles opc (hex) address mode d st s rc opc dst src 6 32 r r 6 33 r lr opc src dst 10 34 r r 10 35 r ir opc dst src 10 36 r im 10 37 ir im
z8 family of microcontrollers user manual instruction description um001602-0904 314 address modes r or ir can be used to specify a 4-bit w orking re gister . in this format, the source or destination w orking re gister operand is speci - ? ed by adding 1110b ( eh ) to the high nibble of the operand. f or e xample, if w orking re gister r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example w orking re gister r3 contains 16h , the c flag is set to 1, and w orking re gister r11 contains 20h , the statement: sbc r3, r11 op code: 32 3b lea v es the v alue f5h in w orking re gister r3. the c, s, and d flags are set, and the z, v , and h flags are all cleared. example if w orking re gister r15 contains 16h , the c flag is not set, w orking re gister r10 contains 20h , and re gister 20h contains 11h , the statement: sbc r16, @r10 op code: 33 fa flag description c cleared if there is a carry from the most significant bit of the result; set otherwise, indicating a borrow . z set if the result is 0; cleared otherwise. v set if arithmetic overflow occurred (if the operands were of opposite sign and the sign of the result is the same as the sign of the source); reset otherwise. s set if the result is negative; cleared otherwise. h cleared if there is a carry from the most significant bit of the low order four bits of the result; set otherwise indicating a borrow . d always set to 1. e src or e dst note:
z8 cpu user manual um001602-0904 instruction description 315 lea v es the v alue 05h in w orking re gister r15. the d flag is set, and the c, z, s, v , and h ? ags are cleared. example :if re gister 34h contains 2eh , the c flag is set, and re gister 12h con - tains 1bh , the statement: sbc 34h , 12h op code: 34 12 34 lea v es the v alue 13h in re gister 34h . the d flag is set, and the c, z, s, v , and h ? ags are cleared. example if re gister 4bh contains 82h , the c flag is set, w orking re gister r3 con - tains 10h , and re gister 10h contains 01h , the statement: sbc 4bh , @r3 op code: 35 e3 4b lea v es the v alue 80h in re gister 4bh . the d flag is set, and the c, z, s, v , and h ? ags are cleared. example if re gister 6ch contains 2ah , and the c flag is not set, the statement: sbc 6ch, #03h op code: 36 6c 03 lea v es the v alue 27h in re gister 6ch . the d flag is set, and the c, z, s, v , and h ? ags are cleared. example if re gister d4h contains 5fh , re gister 5fh contains 4ch, and the c flag is set, the statement: sbc @ d4h , #02h op code: 37 d4 02
z8 family of microcontrollers user manual instruction description um001602-0904 316 lea v es the v alue 4ah in re gister 5fh . the d flag is set, and the c, z, s, v , and h ? ags are cleared.
z8 cpu user manual um001602-0904 instruction description 317 swap nibbles swap dst instruction format operation dst(7-4) ? dst(3-0) the contents of the lo wer four bits and upper four bits of the destination operand are sw apped. address modes r or ir can be used to specify a 4-bit w orking re gister . in this format, destination w orking re gister operand is speci? ed by adding 1110b ( eh ) to the high nibble of the operand. f or e xample, if w orking re gister r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example if re gister bch contains b3h (10110011b), the statement: cycles opc (hex) address mode dst opc dst 6 f0 r 6 f1 ir flag description c unaf fected z set if the result is zero; cleared otherwise. s set if the result bit 7 is set; cleared otherwise. v undefined d unaf fected h unaf fected e dst note:
z8 family of microcontrollers user manual instruction description um001602-0904 318 swap b3h op code: f0 b3 will lea v e the v alue 3bh (00111011b) in re gister bch . the z and s ? ags are cleared. example if w orking re gister r5 contains bch and re gister bch contains b3h (10110011b), the statement: swap @r5h op code: f1 e5 will lea v e the v alue 3bh (00111011b) in re gister bch . the z and s ? ags are cleared.
z8 cpu user manual um001602-0904 instruction description 319 t est complement under mask tcm dst, src instruction format operation (not dst) and src this instruction tests selected bits in the destination operand for a logical 1 v alue. the bits to be tested are speci? ed by setting a 1 bit in the corre - sponding bit position in the source operand (the mask). the tcm instruc - tion complements the destination operand, and then ands it with the source mask (operand). the zero (z) flag can then be check ed to deter - mine the result. if the z flag is set, then the tested bits were 1. when the tcm operation is complete, the destination and source operands still con - tain their original v alues. cycles opc (hex) address mode d st s rc opc dst src 6 62 r r 6 63 r lr opc src dst 10 64 r r 10 65 r ir opc dst src 10 66 r im 10 67 ir im flag description z set if the result is zero; cleared otherwise. s set if the result bit 7 is set; cleared otherwise. v always reset to 0. d unaf fected h unaf fected
z8 family of microcontrollers user manual instruction description um001602-0904 320 address modes r or ir can be used to specify a 4-bit w orking re gister . in this format, the source or destination w orking re gister operand is speci - ? ed by adding 1110b ( eh ) to the high nibble of the operand. f or e xample, if w orking re gister r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example if w orking re gister r3 contains 45h ( 01000101b ) and w orking re gister r7 contains the v alue 01h ( 00000001b ) (bit 0 is being tested if it is 1), the statement: tcm r3, r7 op code: 62 37 will set the z flag indicating bit 0 in the destination operand is 1. the v and s ? ags are cleared. example if w orking re gister r14 contains the v alue f3h ( 11110011b ), w orking re gister r5 contains cbh , and re gister cbh contains 88h ( 10001000b ) (bit 7 and bit 3 are being tested if the y are 1), the statement: tcm r14, @r5 op code: 63 e5 will reset the z flag, because bit 3 in the destination operand is not a 1. the v and s flags are also cleared. example if re gister d4h contains the v alue 04h ( 000001000b ), and w orking re g - ister r0 contains the v alue 80h ( 10000000b ) (bit 7 is being tested if it is 1), the statement: tcm d4h , r0 op code: 64 e0 d4 e src or e dst note:
z8 cpu user manual um001602-0904 instruction description 321 will reset the z flag, because bit 7 in the destination operand is not a 1. the s ? ag will be set, and the v ? ag will be cleared. example if re gister dfh contains the v alue ffh ( 11111111b ), re gister 07h con - tains the v alue 1fh , and re gister 1fh contains the v alue bdh ( 10111101b ) (bit 7, bit 5, bit 4, bit 3, bit 2, and bit 0 are being tested if the y are 1), the statement: tcm dfh, @07h op code: 65 07 df will set the z flag indicating the tested bits in the destination operand are 1. the s and v ? ags are cleared. example if w orking re gister r13 contains the v alue f2h ( 11110010b ), the state - ment: tcm r13, #02h op code: 66 ed, 02 tests bit 1 of the destination operand for 1. the z ? ag will be set indicat - ing bit 1 in the destination operand w as 1. the s and v ? ags are cleared. example if re gister 5dh contains a0h , and re gister a0h contains 0fh ( 00001111b ), the statement: tcm @5d, # 10h op code: 67 5d 10 tests bit 4 of the re gister a0h for 1. the z ? ag will be reset indicating bit 1 in the destination operand w as not 1. the s and v ? ags are cleared.
z8 family of microcontrollers user manual instruction description um001602-0904 322 t est under mask tm dst, src instruction format operation dst and src this instruction tests selected bits in the destination operand for a 0 logi - cal v alue. the bits to be tested are speci? ed by setting a 1 bit in the corre - sponding bit position in the source operand (the mask). the tm instruction ands the destination operand with the source operand (the mask). the zero (z) flag can then be check ed to determine the result. if the z flag is set, then the tested bits were 0. when the tm operation is complete, the destination and source operands still contain their original v alues. cycles opc (hex) address mode d st s rc opc dst src 6 72 r r 6 73 r lr opc src dst 10 74 r r 10 75 r ir opc dst src 10 76 r im 10 77 ir im flag description z set if the result is zero; cleared otherwise. s set if the result bit 7 is set; cleared otherwise. v always reset to 0. d unaf fected h unaf fected
z8 cpu user manual um001602-0904 instruction description 323 address modes r or ir can be used to specify a 4-bit w orking re gister . in this format, the source or destination w orking re gister operand is speci - ? ed by adding 1110b ( eh ) to the high nibble of the operand. f or e xample, if w orking re gister r12 (ch) is the destination operand, then ech will be used as the destination operand in the op code. example if w orking re gister r3 contains 45h ( 01000101b ) and w orking re gister r7 contains the v alue 02h ( 00000010b ) (bit 1 is being tested if it is 0), the statement: tm r3, r7 op code: 72 37 will set the z flag indicating bit 1 in the destination operand is 0. the v and s ? ags are cleared. example w orking re gister r14 contains the v alue f3h ( 11110011b ), w orking re gister r5 contains cbh , and re gister cbh contains 88h ( 10001000b ) (bit 7 a bit 3 are being tested if the y are 0), the statement: tm r14, @r5 op code: 73 e5 will reset the z flag, because bit 7 iin the destination operand is not a 0. the s ? ag will be set, and the v flag is cleared. example if re gister d4h contains the v alue 08h ( 00001000b ), and w orking re g - ister r0 contains the v alue 04h ( 00000100b ) (bit 2 is being tested if it is 0), the statement: tm d4h , r0 op code: 74 e0 d4 e src or e dst note:
z8 family of microcontrollers user manual instruction description um001602-0904 324 will set the z flag, because bit 2 in the destination operand is a 0. the s and v flags will be cleared. example if re gister dfh contains the v alue ( 00000000b ), re gister 07h con - tains the v alue 1fh , and re gister 1fh contains the v alue bdh ( 10111101b ) (bit 7, bit 5, bit 4, bit 3, bit 2, and bit 0 are being tested if the y are 0), the statement: tm dfh, @07h op code: 75 07 df will set the z flag indicating the tested bits in the destination operand are 0. the s is set, and the v flag is cleared. example if w orking re gister r13 contains the v alue f1h ( 11110001b ), the state - ment: tm r13, #02h op code: 76 ed, 02 tests bit 1 of the destination operand for 0. the z ? ag will be set indicat - ing bit 1 in the destination operand w as 0. the s and v ? ags are cleared. example if re gister 5dh contains a0h , and re gister a0h contains 0fh ( 00001111b ), the statement: tm @5d, # 10h op code: 77 5d 10 tests bit 4 of the re gister a0h for 0. the z ? ag will be set indicating bit 4 in the destination operand w as 0. the s and v ? ags are cleared.
z8 cpu user manual um001602-0904 instruction description 325 w atch-dog timer wdt instruction format operation the wdt (w atchCdog t imer) is a retriggerable one shot timer that will reset the z8 ? cpu if it reaches its terminal count. the wdt is initially enabled by e x ecuting the wdt instruction. each subsequent e x ecution of the wdt instruction refreshes the timer and pre v ents the wdt from tim - ing out. the wdt instruction should not be used follo wing an y instruction in which the condition of the ? ags is important. example if the wdt is enabled, the statement: wdt op code: .byte 5fh refreshes the w atchCdog t imer . cycles opc (hex) opc 6 5f flag description z undefined s undefined v undefined d unaf fected h unaf fected note:
z8 family of microcontrollers user manual instruction description um001602-0904 326 example the ? rst e x ecution of the statement: wdt op code: .byte 5fh enables the w atchCdog t imer .
z8 cpu user manual um001602-0904 instruction description 327 w atch-dog timer enable during halt mode wdh instruction format operation when this instruction is e x ecuted it will enable the wdt (w atchCdog t imer) during hal t mode. if this instruction is not e x ecuted the wdt will stop when entering hal t mode. this instruction does not clear the counter , it just mak es it possible to ha v e the wdt function running during hal t mode. a wdh instruction e x ecuted without e x ecuting wdt ( 5fh ) has no ef fect. the wdh instruction should not be used follo wing an y instruction in which the condition of the ? ags is important. example if the wdt is enabled, the statement: wdh op code: .byte 4fh will enable the wdt in hal t mode. cycles opc (hex) opc 6 4f flag description z undefined s undefined v undefined d unaf fected h unaf fected note:
z8 family of microcontrollers user manual instruction description um001602-0904 328 this instruction format is v alid only for the z86c04, z86c08, z86e04, z86e07, and z86e08 mcus. note:
z8 cpu user manual um001602-0904 customer feedback 329 customer feedback if you note any inaccuracies while reading this reference manual , please copy and complete this form, then mail or fax it to zilog (see return information , below). w e also welcome your suggestions! product information customer information return information 532 race street san jose, ca 95126-3432 t elephone: 408.558.8500 fax: 408.558.8300 zilog customer support problem description or suggestion provide a complete description of the problem or your suggestion. if you are reporting a specific prob - lem, include all steps leading up to the occurrence of the problem. attach additional pages as necessary . z8 cpu serial # or board fab #/rev . # software v ersion 1.1.0 document number um001602-0904 host computer description/t ype name country company phone address fax city/state/zip e-mail

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